可規劃技術能使同一套硬體滿足多種規格，而目前所作的可規劃式威特比解碼器主要是對三個控制因子產生多項式、限制長度及碼率作可規劃，但只能對非回授對稱式迴旋編碼和回授對稱式迴旋編碼的其中一種進行解碼，而非回授對稱式迴旋編碼和回授對稱式迴旋編碼是目前最常被使用的通道編碼器，雖然解碼架構並不相同但都是使用威特比解碼器，所以有必要整合它們，本篇論文主要是將非回授對稱式迴旋編碼和回授對稱式迴旋編碼用一個可規劃式威特比解碼器來解碼，除此之外我們還利用分支碼字元組產生器使可規劃的範圍更廣。

The reconfigurable technique can support multiple standards in the same hardware. Now a reconfigurable Viterbi decoder can only decode one of the NSC (Non-systematic and Recursive Systematic Convolutional Codes) and RSC (Systematic and Recursive Systematic Convolutional Codes) encoder. Both NSC and RSC are often used in the channel encoder at present. So, the goal of a reconfigurable Viterbi decoder would be to have the ability to combine the NSC and RSC.
In this thesis, we propose an architecture for a reconfigurable Viterbi decoder that can dynamically adapt to changes in the encoding parameters such as the constraint length, code rate, and generator polynomials. The proposed architecture can be used to realize a reconfigurable Viterbi decoder which can decode the NSC and RSC encoder. Besides, we also use the BCG (Branch Codeword Generator) which can generate the branch codeword to support more applications.

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