研究生: |
莊孟偉 Meng-wei Chuang |
---|---|
論文名稱: |
可規劃式威特比解碼器 A Reconfigurable Viterbi Decoder |
指導教授: |
白宏達
Hung-ta Pai 王乃堅 Nai-jian Wang |
口試委員: |
曾德峰
Der-feng Tseng |
學位類別: |
碩士 Master |
系所名稱: |
電資學院 - 電機工程系 Department of Electrical Engineering |
論文出版年: | 2005 |
畢業學年度: | 93 |
語文別: | 中文 |
論文頁數: | 39 |
中文關鍵詞: | 解碼器 、可規劃 、威特比 |
外文關鍵詞: | reconfigurable.viterbi |
相關次數: | 點閱:173 下載:0 |
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可規劃技術能使同一套硬體滿足多種規格,而目前所作的可規劃式威特比解碼器主要是對三個控制因子產生多項式、限制長度及碼率作可規劃,但只能對非回授對稱式迴旋編碼和回授對稱式迴旋編碼的其中一種進行解碼,而非回授對稱式迴旋編碼和回授對稱式迴旋編碼是目前最常被使用的通道編碼器,雖然解碼架構並不相同但都是使用威特比解碼器,所以有必要整合它們,本篇論文主要是將非回授對稱式迴旋編碼和回授對稱式迴旋編碼用一個可規劃式威特比解碼器來解碼,除此之外我們還利用分支碼字元組產生器使可規劃的範圍更廣。
The reconfigurable technique can support multiple standards in the same hardware. Now a reconfigurable Viterbi decoder can only decode one of the NSC (Non-systematic and Recursive Systematic Convolutional Codes) and RSC (Systematic and Recursive Systematic Convolutional Codes) encoder. Both NSC and RSC are often used in the channel encoder at present. So, the goal of a reconfigurable Viterbi decoder would be to have the ability to combine the NSC and RSC.
In this thesis, we propose an architecture for a reconfigurable Viterbi decoder that can dynamically adapt to changes in the encoding parameters such as the constraint length, code rate, and generator polynomials. The proposed architecture can be used to realize a reconfigurable Viterbi decoder which can decode the NSC and RSC encoder. Besides, we also use the BCG (Branch Codeword Generator) which can generate the branch codeword to support more applications.
[1] B. Sklar,“Digital Communications Fundamentals and Applycations,”Prntrice second edition,pp.437-460,2001.
[2] Viterbi, A.,“Error bounds for convolutional codes and an asymptotically optimum decoding algorithm,”Information Theory, IEEE Transactions on Volume 13, Issue 2, pp.260 – 269, Apr 1967.
[3] Viterbi, A., “Convolutional Codes and Their Performance in Communication Systems,”Communications, IEEE Transactions on [legacy, pre - 1988] Volume 19, Issue 5, pp.751 – 772, Oct 1971.
[4] Ungerboeck, G., “Channel coding with multilevel/phase signals,”Information Theory, IEEE Transactions on Volume 28, Issue 1, pp.55 – 67, Jan 1982.
[5] Ungerboeck, G., “Trellis-coded modulation with redundant signal sets Part II: State of the art”Communications Magazine, IEEE Volume 25, Issue 2, pp.5 – 11,Feb 1987.
[6] Ungerboeck, G., “Trellis-coded modulation with redundant signal sets Part I: Introduction”Communications Magazine, IEEE Volume 25, Issue 2, pp. 12 - 21,Feb 1987.
[7] 李巂儀, “實用型格狀編碼調變系統效能模擬”1999.
[8] “Digital Video Broadcasting (DVB);Framing structure, channel coding and modulation for digital terrestrial television“ETSI EN 300 744 V1.5.1,Nev. 2004.
[9] “Radio Broadcasting Systems;Digital Audio Broadcasting (DAB) to mobile, portable and fixed receivers” ETSI EN 300 401 V1.3.2,Sep. 2000.
[10] Interaction channel using global system for mobile communications (GSM)” BT.1508 ,Oct. 2000.
[11] “IEEE Standard for Local and Metropolitan Area Networks Part 16: Air Interface for Fixed Broadband Wireless Access Systems,” IEEE Std 802.16-2004 (Revision of IEEE Std 802.16-2001),2004.
[12] “ATSC Standard A/53C with Amendment No. 1 and Corrigendum No. 1:
ATSC Digital Television Standard, Rev. C,”May. 2004.
[13] “Asymmetric Digital Subscriber Line (ADSL) transceivers - Extended bandwidth ADSL2 (ADSL2+)” G.992.5,Jan. 2005.
[14] Heller, J.; Jacobs, I. “Viterbi Decoding for Satellite and Space Communication,”Communications, IEEE Transactions on [legacy, pre - 1988] Volume 19, Issue 5, pp.835 – 848, Oct 1971.
[15] G. DAVID FORNEY ,JR., “The Viterbi Algorithm,”Processdings of the IEEE,Vol. 61,No.3,Mar. 1973.
[16] Cain, J.; Clark, G.; Geist, J., “Punctured convolutional codes of rate(n-1)/nand simplified maximum likelihood decoding (Corresp.),” Information Theory, IEEE Transactions on,Volume 25, Issue 1, pp.97 – 100,Jan 1979
[17] Lou, H.-L., “Implementing the Viterbi algorithm” Signal Processing Magazine, IEEE Volume 12, Issue 5, pp.42 – 52,Sept. 1995
[18] Gulak, P.; Shwedyk, E., “VLSI Structures for Viterbi Receivers: Part I--General Theory and Applicationsb” Selected Areas in Communications, IEEE Journal on Volume 4, Issue 1, pp.142 – 154,Jan 1986
[19] Gulak, P.G.; Kailath, T., “Locally connected VLSI architectures for the Viterbi algorithm”Selected Areas in Communications, IEEE Journal on Volume 6, Issue 3, pp.527 – 537, April 1988.
[20] Black, P.J.; Meng, T.H. “,A 140-Mb/s, 32-state, radix-4 Viterbi decoder;” Solid-State Circuits, IEEE Journal of Volume 27, Issue 12, pp.1877 – 1885,Dec. 1992.
[21] RICHARD B. WELLS, “Applied Coding and Information Theory for Engineers,”Prentice Hall,pp.210-238,1999.
[22] HONG-DAR LIN,C.BEMARD SHUNG, and DAVID G. MESSERSCHMITT ,“Folded Viterbi Decoders for Convolutional Codes,” Vlsi IV,1990.
[23] Kelly, P.H.; Chau, P.M., “A flexible constraint length, foldable Viterbi decoder,” Global Telecommunications Conference, 1993, including a Communications Theory Mini-Conference. Technical Program Conference Record, IEEE in Houston. GLOBECOM '93.,pp.631 – 635, Dec. 1993.
[24] Chadha, K.; Cavallaro, J.R.,“A reconfigurable Viterbi decoder architecture,”Signals, Systems and Computers, 2001. Conference Record of the Thirty-Fifth Asilomar Conference on Volume 1, 4-7 pp.66 - 71 vol.1, Nov. 2001.
[25] Chadha, K., “A Reconfigurable Decoder Architecture for Wireless LAN and Cellular System,”2001.
[26] 黃品玄,“可規劃式威特比解碼器之設計”2001.
[27] RICHARD B. WELLS, “Applied Coding and Information Theory for Engineers,”Prentice Hall,pp.133-135,1999.
[28] Rader, C., “Memory Management in a Viterbi Decoder,” Communications, IEEE Transactions on [legacy, pre - 1988] Volume 29, Issue 9, pp.1399 – 1401, Sep 1981 .
[29] Feygin, G.; Gulak, P.G., “Survivor sequence memory management in Viterbi decoders, “Circuits and Systems, 1991., IEEE International Sympoisum on 11-14 June 1991 Page(s):2967 - 2970 vol.5
[30] Black, P.J.; Meng, T.H.-Y., “Hybrid survivor path architectures for Viterbi decoders,”Acoustics, Speech, and Signal Processing, 1993. ICASSP-93., 1993 IEEE International Conference on Volume 1, pp.433 – 436, 27-30 April 1993.
[31] Feygin, G.; Gulak, P., “Architectural tradeoffs for survivor sequence memory management in Viterbi decoders” Communications, IEEE Transactions on Volume 41, Issue 3, pp.425 – 429,March 1993 .