本篇論文提出了三顆不同結構的注入鎖定除頻器，分別為三頻帶除二注入鎖定除頻器、單頻帶除四注入鎖定除頻器以及雙頻帶除二注入鎖定除頻器。
首先，第一顆晶片是使用台積電(TSMC) SiGe 0.18 um 製程來實現的三頻帶注入鎖定除頻器，這顆除頻器的設計方式是用交叉耦合(cross couple)與並聯可調共振腔之振盪器，加上由主被動元件混合組成的線性混波器。當驅動偏壓為 0.9 V且注入訊號強度為 0 dBm時，使用偏壓令兩個除頻頻帶合而為一，可接受注入訊號從 2.65 GHz 到 9.89 GHz ，鎖定範圍總共7.24 GHz，除頻比例為115.47%，且在極弱的注入強度下(-20 dBm)仍能有注入頻率由3.7到7.6GHz的除頻範圍，對應比率為 69.03% 。此晶片的核心電流為9.65mA，功耗為8.685mW，所占面積是0.726 × 0.930 mm2。
其次，第二顆晶片我們使用台積電(TSMC) 0.18 um製程實現一個除四注入鎖定除頻器，此除頻器設計則是基於一電容耦合的壓控振盪器，接著使用兩個MOSFETs閘極互接做為注入；此除頻器的驅動偏壓為1.2V，以 0 dBm的注入強度當作輸入信號源，除頻範圍為 35.89% ，所對應到的注入頻率為 7.43到10.68 GHz 共 3.25GHz ，此除頻器的核心電流為 9.858mA，功率消耗為11.83mW。晶片總面積為0.883 × 0.851mm2。
最後，第三顆晶片是一個雙頻帶注入鎖定除頻器，同樣使用台積電(TSMC) 0.18 um製程來實現，設計架構使用兩個串連電晶體做為注入，並包含一組RLC雙頻共振腔，其中使用了一組電阻來加寬除頻範圍；在驅動電壓1.1V、注入強度0 dBm下，除二範圍總共為6.7GHz，注入頻率從3.0GHz到7.1GHz，總除頻比率為105.51%，除頻器的核心功耗共12.32mW。晶片面積0.758 × 0.822mm2。

First, a wide locking range divide-by-2 RLC injection-locked frequency divider (ILFD) was designed and implemented in the TSMC 0.18 μm BiCMOS process. The ILFD is based on a cross-coupled oscillator with one direct injection MOSFET and a RLC resonator. The RLC resonator is used to extend the locking range so that dual-band locking ranges can be merged in one locking range at both low and high injection power. At the drain-source bias of 0.9 V, and at the incident power of 0 dBm, the locking range of the divide-by-2 ILFD is 7.24 GHz, for the incident frequency ranging from 2.65 to 9.89 GHz, and the locking range percentage is 115.47%. The power consumption of ILFD core is 8.685 mW. The die area is 0.726 × 0.930 mm2.
Secondly, we proposes an ultra wide locking range divide-by-4 ILFD implemented in the TSMC 0.18 μm 1P6M CMOS process. The ILFD uses a Class-C capacitive cross-coupled voltage-controlled oscillator (VCO) with two direct injection MOSFETs sharing a common injection gate. The dc gate bias of cross-coupled FETs is smaller than dc drain bias. At the drain-source bias of 1.2 V and at the incident power of 0 dBm, the measured locking range of the divide-by-4 ILFD is 3.25 GHz for the incident frequency extending from 7.43 to 10.68 GHz. The locking range percentage is 35.89％. The core power consumption is 11.83 mW. The die area is 0.883 ×0.851mm2.
Finally, we presents a wide locking range divide-by-2 RLC injection-locked frequency divider (ILFD) implemented in the TSMC 0.18 μm 1P6M CMOS process. The ILFD is based on a cross-coupled oscillator with two direct injection MOSFETs in series and a dual-resonance RLC resonator. The resistor is used to enhance the locking range. At the drain-source bias of 1.1 V and at the incident power of 0 dBm, the locking range of the divide-by-2 ILFD is 6.7 GHz, for the incident frequency 3.0 extending to 9.7 GHz. The locking range percentage is 105.51%. The power consumption of ILFD core is 12.32 mW. The die area is 0.758 × 0.822 mm2.

[1] B. Razavi, “RF Microelectronics”, Upper Saddle River, NJ: Prentice Hall, 1998
[2] N. M.Nguyen and R. G. Meyer, “Start-up and frequency stability in high-frequency oscillators,” IEEE J. Solid-State Circuit, vol. 27, no. 5, pp. 810–820, May 1992.
[3] B. Razavi, “Design of Analog CMOS Integrated Circuit”, McGraw Hill, 2008.
[4] G. Gonzalez , “Microwave Transistor Amplifiers Analysis And Design,” Prentice Hall, 1997
[5] B.Razavi, “Design of Integrated Circuits for Optical Communications”, McGraw Hill.
[6] S.J. Lee, B. Kim, K. Lee, “A Novel High-Speed Ring Oscillator for Multiphase Clock Generation Using Negative Skewed Delay Scheme,” IEEE Journal of Solid-State Circuits, vol. 32, No. 2, February 1997.
[7] 劉隽宇, 翁若敏, “運用於IEEE 802.11a CMOS 頻率合成器的低雜訊寬調變範圍之壓控振盪器,” 2005.07.
[8] 李少華, 張勝良, “Implementation of New High Frequency CMOS VCOs and Injection-Locked Frequency Dividers,” 2007 04.
[9] Hajimiri, and T. H. Lee, “The design of low noise oscillators,” Kluwer Academic Publishers, 1999
[10] De Muer, M. Borremans, M.Steyaert, and G. Li Puma, “A 2GHz low-phase-noise integrated LC-VCO set with flicker-noise upconversion minimization,” IEEE J. Solid-State Circuits, vol. 35, pp. 1034-1038, 2000.
[11] S.Levantino, C.Samori, A.Bonfanti, S.L.J. Gierkink, A.L. Lacaita, and V. Boccuzzi, “frequency dependence on bias current in 5 GHz CMOS VCOs: impact on tuning range and flicker noise upconversion,” IEEE J. Solid-State Circuits, vol. 37, pp. 1003-1001, 2002.
[12] T. H. Lee, The Design of CMOS Radio Frequency Integrated Circuits, Cambridge University Press 1998.
[13] H. M. Greenhouse, “Design of planar rectangular microelectronic inductors,” IEEE Transactions on Parts, Hybrids, and Packaging, vol. 10, pp. 101-109, Jun 1974.
[14] J. Craninckx and M. S. J. Steyaert, “A 1.8 GHz low-phase-noise CMOS VCO using optimized hollow spiral inductors,” IEEE J. Solid-State Circuits, vol. 32, no. 5, pp. 736–744, May 1997.
[15] C. P. Yue, C. Ryu, JackLau, T. H. Lee, and S. Wong, “A physical model for planar spiral inductors on silicon,” 1996 International Electron Devices Meeting Technical Digest, pp. 155–158, Dec. 1996.
[16] J. R. Long, “Monolithic transformers for silicon RF IC design,” IEEE Journal of Solid-State Circuits, vol. 35, pp. 1368-1382, Sept. 2000.
[17] E. Frlan, S. Meszaros, M. Cuhaci, and J.Wight, “Computer-aided design of square spiral transformers and inductors,” in Proc. IEEE MTT-S, pp. 661-664, June 1989.
[18] P. Andreani, S. Mattisson, “On the use of MOS varactors in RF VCOs,” IEEE Journal of Solid-State Circuits, vol. 35, no. 6, pp. 905-910, June 2000.
[19] J. van der Tang, and D. Kasperkovitz, “Oscillator design efficiency: a new figure of merit for oscillator benchmarking,” IEEE International Symposium on Circuit and System (ISCAS), vol. 2, pp. 533-536, May 2000.
[20] J.J. Rael, and A. A. Abidi, “Physical processes of phase noise in differential LC oscillators,” IEEE Custom Integrated Circuits Conference, pp. 569–572, 2000.
[21] T. Lee and A. Hajimiri, “Oscillator phase noise: a tutorial,” IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 326–336, Mar. 2000.
[22] D. Leeson, “A simple model of feedback oscillator noise spectrum,” Proceedings of the IEEE, vol. 54, pp. 329–330, Feb. 1966.
[23] Hajimiri and T. H. Lee, “A general theory of phase noise in electrical oscillators,” IEEE J. Solid-State Circuits, vol. 33, no. 2, pp. 179–194, Feb. 1998.
[24] Hajimiri and T. H. Lee, “Design Issues in CMOS differential LC Oscillators,” IEEE J. Solid-State Circuits, vol. 34, pp. 717–724, May 1999.
[25] J. Craninckx and M. S. J. Steyaert, “A 1.75-GHz/3-V dual-modulus divide-by-128/ 129 prescaler in 0.7 um CMOS,” IEEE J. Solid-State Circuits, vol. 31, pp. 890-897, July 1996.
[26] J. Tang and D. Kasperkovitz, Oscillator Design Efficiency: A New Figure Of Merit For Oscillator Benchmarking.
[27] S. H. Lee, S. L. Jang, and Y. H. Chung, “A low voltage divide-by-4injection locked frequency divider with quadrature outputs,” IEEE Microw. Wireless Compon. Lett., vol. 17, no. 5, pp. 373–375, May 2007.
[28] K. Yamamoto and M. Fujishima, “70 GHz CMOS harmonic injectionlockeddivider,” in IEEE Int. Solid-State Circuits Conf. Dig.,pp. 2472–2481, Feb. 2006.
[29] Voinigescu, S. P., D. Marchesan, and M. A. Copeland, “Family of Monolithic Inductor-Varactor SiGe-HBT VCOs for 20-GHz to 30-GHz LMDS and fiber-optic receiver applications, ” RFIC Symp. Digest, pp.173-176, Jun 2000.
[30] M. Tiebout, A CMOS direct injection-locked oscillator topology as high-frequency low-power frequency divider, IEEE J. Solid-State Circuits,vol. 39, no. 7, pp. 1170–1174, Jul. 2004.
[31] K. Yamamoto and M. Fujishima, “55GHz CMOS frequency dividerwith 3.2GHz locking range,” ESSCC, pp. 135-138, Aug., 2004.
[32] Buonomo, A. Lo Schiavo, M. Asfandyar Awan, M. Summair Asghar, M. Peter Kennedy, “A CMOS injection-locked frequency divider optimized for divide-by-two and divide-by-three operation,” IEEE Trans. Circuits and Systems 60-I(12): 3126-3135 (2013).
[33] Plessas F. “A study of superharmonic injection locking in multiband frequency dividers.” Int. J. Circ. Theor. Appl. 39:397–410, 2011.
[34] Z.-D. Huang, C.-Y. Wu, and B.-C. Huang, “Design of 24-GHz 0.8-V 1.51-mW coupling current-mode injection-locked frequency divider with wide locking range,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 8, pp. 1948–1958, Aug. 2009.
[35] Buonomo and A. Lo Schiavo, “Nonlinear dynamics of divide-by-two injection-locked frequency dividers in locked operation mode,” Int. J. Circ. Theor. Appl., vol. 42, no. 8, pp. 794–807, 2013.
[36] H. Wu and A. Hajimiri, “A 19 GHz 0.5mW 0.35 μm CMOS frequencydivider with shunt-peaking locking-range enhancement,” IEEE Int.Solid-State Circuits Conf., pp. 412-413, Feb. 2001.
[37] Y.-H. Chuang, S.-H. Lee, R.-H. Yen, S.-L. Jang, J.-F. Lee and M.-H. Juang, A wide locking range and low voltage CMOS direct injection-locked frequency divider, IEEE Microw. Wireless Compon. Lett., vol. 16, no. 5, pp. 299-301, May 2006.
[38] S.-L. Jang, Z.-H. Wu, C.-W. Hsue and H.-F. Teng, “Wide-locking range dual-band injection-locked frequency divider,” Microw. Opt. Technol. Lett. vol. 55, 10, pp. 2333–2337, October 2013.
[39] S.-L. Jang, L.-Y. Huang, C.-W. Hsue, and J.-F. Huang, “Injection-locked frequency divider using injection mixer DC-biased in sub-threshold,” IEEE Microw. Wireless Compon. Lett., vol. 25, no. 3, pp. 193-195, March 2015.
[40] H. R. Rategh and T. H. Lee, “Superharmonic injection-locked frequency dividers,” IEEE J. Solid-State Circuits, vol. 34, no. 6, pp. 813–821, June 1999.
[41] J. Lee and B. Razavi, “A 40 GHz frequency divider in 0.18-μm CMOS technology,” Symp. VLSI Circuits Dig. Tech. Papers, June 2003, pp. 259–262.
[42] S.-L. Jang, S.-S. Huang, J.-F. Lee and M.-H. Juang, “LC-tank Colpitts injection-locked frequency divider with record locking range,” IEEE Microw. Wireless Compon. Lett., pp.560-562, Aug. 2008.
[43] S. Lee, S. Jang, and C. Nguyen, “Low-power-consumption wide-locking-range dual-injection-locked 1/2 divider through simultaneous optimization of VCO loaded Q and current,” IEEE Trans. Microw. Theory Tech., vol. 60, no. 10, pp. 3161–3168, Oct. 2012.
[44] N. Mahalingam, K. Ma, K. S. Yeo, and W. M. Lim, “Coupled dual LC tanks based ILFD with low injection power and compact size,” IEEE Microw. Wireless Compon. Lett., vol. 24, no. 2, pp. 105-107, Feb 2014.
[45] S.-L. Jang, F.-B. Lin,and J.-F. Huang, “Wide-band divide-by-2 injection-locked frequency divider using MOSFET mixers DC-biased in subthreshold region,” Int. J. Circ Theor App, 12, Jan. 2015.
[46] S. H. Lee, S. L. Jang, and Y. H. Chung, “A low voltage divide-by-4injection locked frequency divider with quadrature outputs,” IEEE Microw.Wireless Compon. Lett., vol. 17, no. 5, pp. 373–375, May 2007.
[47] S.-L. Jang,C. C. Liuand C.-W. Chung, “A tail-injected divide-by-4 SiGe HBT injection locked frequency divider,” IEEE Microw. Wireless Compon. Lett., vol.19,no. 4,pp. 236-238, April 2009.
[48] S.-L. Jang, C.-H. Liu, C.-W. Chang, and M.-H. Juang," A low voltage, low power divide-by-4 LC-tank injection-locked frequency divider, " Int. J. Electronics., vol. 98,no. 4, pp. 521-527, April 2011.
[49] S.-L. Jang, H.-F. Teng, S.-S. Tzeng and C.-W. Hsue, “Degeneration of over-voltage stress CMOS divide-by-4 injection-locked frequency divider,” ISNE, 2014.
[50] L. Wu and H. C. Luong, “Analysis and design of a 0.6 V 2.2 mW 58.5-to-72.9 GHz divide-by-4 injection-locked frequency divider with harmonic boosting,” IEEE Trans. Circuits and Systems-Part I, Regular Papers, vol. 60, no. 8, pp. 2001-2008, Nov. 2013.
[51] C.-W. Chang, S.-L. Jang, and M.-H. Juang, “Divide-by-4 injection-locked frequency divider using two linear mixers,” Microw. Opt. Technol. Lett., pp.1359-1362, June, 2012.
[52] C.-W. Chang and S.-L. Jang,” A differential BiCMOS divide-by-4 injection-locked frequency divider,” Microw. Opt. Technol. Lett.. vol. 54, pp.2825-2828, Dec., 2012.
[53] C.-W. Chang and S.-L. Jang,” LC-Tank divide-by-4 injection-locked frequency divider using the 2nd harmonic feedback,” Int. J. Electronics., vol. 101,no. 2, pp. 204-211, 2014.
[54] S.-L. Jang, Y.–T. Chang, C.-W. Hsue, and M.-H. Juang, ” Wide-locking range divide-by-4 injection-locked frequency divider using injection MOSFET DC-biased above threshold region,” accepted June 2015, int. j. circ. theor. appl
[55] S.-L. Jang, and C.-C. Fu. “Wide locking range divide-by-4 LC-tank injection-locked frequency divider using series-mixers,” Analog Integr Circ Sig Process, vol. 78, issue 2, pp. 523–528, Feb. 2014.
[56] S.-L. Jang, J.-F. Huang and F.-B. Lin,” Wide-locking range LC-tank divide-by-4 injection-locked frequency divider using transformer feedback,” Int. J. RF Microwave Computer-Aided Design., accepted. 2015.
[57] S.-L. Jang, and C.-Y. Lin, ” A wide-locking range Class-C injection-locked frequency divider,” Electronics Letters .,vol. 50, 23, pp.1710-1712, 2014.
[58] Razavi, "A study of injection locking and pulling in oscillators," IEEE J. Solid-State Circuits, 39(9):1415-1424, Sept. 2004.