本論文使用TSMC 0.18μm CMOS製程，設計兩個應用於不同頻率及系統的無線接收器前端射頻電路，第一個電路頻率操作在900 MHz，電路可應用於RFID系統和GSM系統。電路操作電壓為1.8伏特，消耗的功率是15 mW。電路的內容是設計一個低雜訊放大器連接混頻器，接收到微弱的高頻訊號之後首先低雜訊放大器會將訊號放大，再經過混頻器將訊號放大及降頻，降頻後的中頻訊號頻率為400 kHz。第二個電路頻率操作在433 MHz，電路是應用於生醫系統。電路的操作電壓為1.2伏特，消耗的功率是505 μW。電路設計的內容與第二個電路相同，也是一個低雜訊放大器連接混頻器，混頻器降頻後的中頻訊號為20 kHz。
另外做了改善第一個電路效能的設計，這個設計著重於電路線性度還有穩定度的改良，並增加一個簡單的壓控振盪器，不但改善了外接本地訊號可能造成相位誤差的問題，也省去了外接本地訊號的麻煩；電路消耗與原來電路相差不多的功率(改良電路新增了壓控振盪器)但線性度已改善許多。

This thesis presents two designs of radio frequency (RF) receiver front end circuits for different applications utilizing TSMC CMOS 0.18μm process. The first front end circuit operates at 900 MHz and can be applied to RFID and GSM systems. This front end operates at 1.8 V with a power consumption of 15 mW. The front end circuit consists of a low noise amplifier (LNA) and a mixer. After receiving a small high-frequency signal, the mixer amplifies and down-converts the signal amplified by the LNA into a 400 kHz medium-frequency signal. The second front end operates at 433 MHz, and is for biomedical systems. This front end operates at 1.2 V with a power consumption of 505 μW. The structure is the same as the previous one, also an LNA and a mixer. The mixer in this circuit down-converts the input signal to a medium-frequency signal of 20 kHz.
In addition, this thesis also made improvements for the first front end circuit. The improved circuit emphasizes on better linearity and better stability. Moreover, a simple voltage controlled oscillator (VCO) is added. This modification not only solves the problem of phase error caused by using external local oscillator signals (LO), but also saves the trouble of finding and connecting an external LO. The modified front end has nearly the same power consumption as the original, but has much better linearity.

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