使用協同技術提升隨機存取記憶體的良率和可靠度｜國立臺灣科技大學博碩士論文系統

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研究生：	黃煥華 Huan-Hua Huang
論文名稱：	使用協同技術提升隨機存取記憶體的良率和可靠度 Synergistic Techniques for Yield and Reliability Enhancement of Random Access Memories
指導教授：	呂學坤 Shyue-Kung Lu
口試委員:	李建模 Chien-Mo Li 李進福 Jin-Fu Li 黃錫瑜 Shi-Yu Huang 姚嘉瑜 Chia-Yu Yao
學位類別：	碩士 Master
系所名稱：	電資學院 - 電機工程系 Department of Electrical Engineering
論文出版年：	2011
畢業學年度：	99
語文別：	英文
論文頁數：	80
中文關鍵詞：	協同技術、隨機存取記憶體、良率、可靠度
外文關鍵詞：	Synergistic techniques, yield, reliability, random access memory
相關次數：	點閱：272 下載：6
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根據製程廠所得到的點陣圖結果,出現在嵌入式記憶體裡的錯誤大約有60%—70%的錯誤是屬於正交錯誤. 如我們所知,每一個正交錯誤都需要一條備用列或欄來做修復.若發生大量的正交錯誤,我們需使用大量的備用元件來去做修復. 因此,若我們沒有足夠的備用資源,修復率和製程良率將會下降. 因此,在這篇論文裡提出了協同技術取代了傳統的錯誤取代技術, 利用整合錯誤取代和錯誤遮蔽技術來提升良率和可靠度.在我們的方法裡, 當我們寫入一個錯誤的值到記憶體裡,正交錯誤會被遮蔽掉.(比如,錯誤效應沒有被激發起來).因此,我們需選擇寫入原本的資料還是將這筆資料做互補後來再寫入含有正交錯誤的記憶體列裡.而一條儲存著控制位元的控制欄也會被加入到記憶體陣列裡.依據每一記憶裡列所對應的控制位元來決定讀出的資料要直接用還是要經過反轉再讀出.對於其餘的錯誤型態(除了正交錯誤),則使用錯誤取代技術來修復.另外,以協同技術為基底,所對應的內建自我修復架構也被提出來. 根據模擬結果,當正交錯誤所含的比例占全部錯誤的90%時,修復率可以高達85.6%.此外,因為硬體額外所需的成本只占全部的0.405%且performance penalty在做寫入的動作時,最多只花120ns,而讀取時最多只花40ns.因此這些額外的負擔幾乎都是可略的.

According to bitmap results from the foundry, orthogonal faults stand for about 60-70% of the total number of defects occurring in embedded memories. As we know, orthogonal faults are rather redundancy hungry since a spare row/column is required for repairing each orthogonal fault. Therefore, repair rate and manufacturing yield will decrease if we do not allocate sufficient spare resources. Therefore, instead of the traditional fault replacement techniques, synergistic techniques which integrate both fault replacement and fault masking techniques are proposed in this paper for yield and reliability enhancement. With our approaches, orthogonal faults are masked if we write its faulty value into it (i.e., the faulty effects are not activated). Therefore, we should choice to write the original data or their complement into the memory rows containing orthogonal faults. A control column which stores control bits is added for the memory array. Depending on the value of the control bit for a memory row, the read out data can be used directly or complemented before usage. For other minor fault types (except orthogonal faults), the fault replacement technique is used. Based on the synergistic techniques, the corresponding built-in self-repair architectures are proposed. According to simulation results, repair rates can be achieved 85.6% when orthogonal faults occupy 90% of total faults. Moreover, since the hardware overhead is only 0.405% and performance penalty is 40ns, they can be almost negligible.

Abstract (in Chinese)
Abstract
Acknowledgement (in Chinese)
Contents
List of Figures
List of Tables
Introduction
1 Motivation and Background
2 Organization
Basic Concepts of BIST, BISD, and BISR Techniques for Embedded Memories
1 RAM Static Fault Models
2 RAM Test Algorithms
3 Built-In Self-Test and Build-In Self-Diagnosis
4 Built-In Redundancy Analysis and Built-In Self-Repair
4.1 Built-In Redundancy Analysis
4.1.1 Comprehensive Real-time Exhaustive Search Test and Analysis (CRESTA) Algorithm
4.1.2 Repair Most ( RM ) Algorithm
4.1.3 Local Repair Most ( LRM ) Algorithm
4.1.4 Essential Spare Pivoting ( ESP ) Algorithm
4.1.5 Extended Essential Spare Pivoting ( EESP ) Algorithm
4.2 Built-In Self-Repair
4.2.1 Built-In Self-Repair Scheme with 2-D Redundancies
4.2.2 Built-in Self-Repair Scheme for Multiple Repairable RAMs
Fundamentals of Error Correction Codes
1 Hamming Code
2 Hsiao Code
3 Error Correction Codes with Minimal Triple Bit Error Miscorrection Rates
Synergistic Reliability Yield Enhancement Techniques
1 Introduction
2 Redundancy Architecture
3 Synergistic Repair Schemes with ECC and Redundancy
4 Synergistic Architectures
5 The Implementation of BIST and BIRA Circuit
5.1	The Bist Circuit
5.2	The BIRA Circuit
6 Synergistic Essential Spare Pivoting (SESP) Algorithm
7 An Example of SESP Algorithm
Experimental Results
1 Defect Distribution and Fault Models
2 Repair Rate Analysis
3 Hardware Overhead Analysis
4 Performance Penalty
5 Implementation of the Synergistic BISR Architectures
Conclusions and Future Works
1 Conclusions
2 Future Works
References

                                

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