本論文提出一個實現於現場可程式化閘陣列(field programmable gate array, FPGA)並能夠抵抗製成、電壓與溫度(process-voltage-temperature, PVT)變異的時間至數位轉換電路(Time-to-digital converter, TDC)。本論文之TDC不但可以抵抗PVT變異，並且可以達到高解析度與寬的量測時間範圍。經過FPGA內建的鎖相迴路提供八個不同的相位，達到84微微秒不受PVT變異影像的解析度，另外並加入偏移校準技術更進一步的抵抗PVT變異對偏移量的影響。經過短線量測之後量測出本論文之TDC的差分非線性誤差為-0.482~0.457LSB；積分非線性誤差為-0.612~0.575LSB。並完整測試涵蓋0℃到50℃的運作功能驗證本TDC對抗溫度變異之效果。

A process-voltage-temperature (PVT) insensitive time-to-digital converter (TDC) implemented on field programmable gate array (FPGA) is presented. The proposed TDC is aimed to provide a PVT-insensitive TDC solution with high resolution and wide measurement range. With the aid of the phase locked loop (PLL) on the FPGA which provides 8 different phases, the resolution of about 84 ps can be predefined and unchanged against PVT variations. The proposed TDC successfully eliminates the offset adjustment with a simple offset cancelation technique. The short-term measurement differential nonlinearity (DNL) of this TDC is -0.482 ~ 0.457 LSB, and the integral nonlinearity (INL) is -0.612 ~ 0.575 LSB. This TDC was tested to be fully functional over 0℃ to 50℃ ambient temperature range with extremely low resolution variations.

[1]A. H. Chan and G. W. Roberts, “A jitter characterization system using a component-invariant Vernier delay line,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 1, pp. 79–95, Jan. 2004.

[2] K. Ealgoo, L. Hansang, L. Taeyon, C. Dongbum, and P. Jaehong, “Time of flight (TOF) measurement of adjacent pulses,” in IEEE Nucl. Sci. Symp. Conf. Rec., vol. 2, pp. 609–612, 2001.

[3] K. Maatta and J. Kostamovaara, “A high-precision time-to-digital converter for pulsed time-of-flight laser radar applications,” IEEE Trans. Instrum. Meas., vol. 47, no. 2, pp. 521–536, 1998.

[4] N. Paschalidis et al., “A time-of-flight system on a chip suitable for space instrumentation,” in IEEE Nucl. Sci. Symp. Conf. Rec., vol. 2, pp. 750–754, 2001.

[5] P. Palojarvi, K. Maatta, and J. Kostamovaara, “Integrated time-of-flight laser radar,” IEEE Trans. Instrum. Meas., vol. 46, no. 4, pp. 996–999, 1997.

[6] H. Brockhaus and A. Glasmachers, “Single particle detector system for high resolution time measurements,” IEEE Trans. Nucl. Sci., vol. 39, no. 4, pp. 707–711, 1992.

[7] R.W. Necoecha, “High performance monolithic verniers for VLSI automatic test equipment,” Proceedings International Test Conference, pp. 422-430, 1992.

[8] T. Otsuji, “A picoseconds-accurary,700-Mhz range si-bipolar time interval counter LSI,” IEEE Journal of Solid-State Circuit, vol. 28, pp. 941-947, 1993.

[9] P. Napolitano, A. Moschitta, P. Carbone, “A survey on time interval measurement techniques and testing methods,” IEEE International Instrumentation and Measurement Technology Conference, I2MTC 2010 - Proceedings , art. no. 5488103, pp. 181-186, 2010.

[10] R. Nutt, “Digital time intervalometer,” Rev. Sci. Instrum, vol. 39, no. 9, pp. 1342-1345, 1968.

[11] J. Kalisz, R. Szplet, J. Pasierbinski, A. Poniecki, “Field-programmable-gate-array-based time-to-digital converter with 200-ps resolution,” IEEE Trans. Instrum. Meas., vol. 46, pp. 71-75, 1997.

[12] J. Kalisz, R. Szplet, R. Pelka, A. Poniecki, “Single-chip interpolating time counter with 200-ps resolution and 43-s range,” IEEE Trans. Instrum. Meas., vol. 46, pp. 851-856, 1997.

[13] M.S. Andaloussi, M. Boukadoum, E.M. Aboulhamid, “A novel time-to-digital converter with 150 ps time resolution and 2.5 ns pulse-pair resolution,” Microelectronics, The 14th International Conference on 2002 – ICM, pp. 123-126, 2002.

[14] A.M. Amiri, M. Boukadoum, A. Khouas, “A Multihit Time-to-Digital Converter Architecture on FPGA,” IEEE Trans. Instrum. Meas., vol. 58, pp. 530-540, 2009.

[15] J. Wu, Z. Shi, I.Y. Wang, “Firmware-only Implementation of Time-to-Digital Converter (TDC) in Field-Programmable Gate Array (FPGA),” IEEE Nuclear Science Symposium Conference Record, 1, art. no. N10-2, pp. 177-181, 2003.

[16] J. Song, Q. An, S. Liu, “A High-Resolution Time-to-Digital Converter Implemented in Field-Programmable-Gate-Arrays,” IEEE Trans. on Nuclear Science, Vol. 53, pp. 236-241, 2006.

[17]A. Aloisio, P. Branchini, R. Giordano, V. Izzo, S. Loffredo, “High-precision Time-to-Digital Converter in a FPGA device,” IEEE Nuclear Science Symposium Conference Record, art. no. 5401744, pp. 290-294, 2009.

[18] J. Wang, S. Liu, Q. Shen, H. Li, Q. An, “A Fully Fledged TDC Implemented in Field-Programmable Gate Arrays,” IEEE Trans. on Nuclear Science, vol. 57, art. no. 5446507, pp. 446-450, 2010.

[19] J. Wu, Z. Shi, “The 10-ps wave union TDC: Improving FPGA TDC resolution beyond its cell delay,” IEEE Nuclear Science Symposium Conference Record, art. no. 4775079, pp. 3440-3446, 2008.

[20] R. Pelka, J. Kalisz, R. Szplet, “Nonlinearity correction of the integrated time-to-digital converter with direct coding,” IEEE Trans. Instrum. Meas. vol. 46, pp. 449-453, 1997.

[21] M.D. Fries, J.J. Williams, “High-Precision TDC in an FPGA using a 192-MHz Quadrature Clock,” IEEE Nuclear Science Symposium and Medical Imaging Conference, vol. 1, pp. 580-584, 2002.

[22] 林灶生, 劉紹漢, “Verilog FPGA晶片設計,” 全華圖書股份有限公司, 2005.

[23] R. Szplet, K. Klepacki, “An FPGA-integrated time-to-digital converter based on two-stage pulse shrinking,” IEEE Trans. Instrum. Meas., vol. 59, art. no. 5280372, pp. 1663-1670, 2010.

[24] S.S. Junnarkar, P. O'Connor, P. Vaska, R. Fontaine, “FPGA-based self-calibrating time-to-digital converter for time-of-flight experiments,” IEEE Transactions on Nuclear Science, vol. 56, art. no. 5204613, pp. 2374-2379, 2009.

[25] P. Chen, M.-C. Shie, Z.-Y. Zheng, Z.-F. Zheng and C.-Y. Chu, “A Fully Digital Time Domain Smart Temperature Sensor Realized with 140 FPGA Logic Elements,” IEEE Transactions on Circuits and Systems I, Vol.54, pp. 2661-2668, 2007.

[26] Poki Chen, Po-Yu Chen, Juan-Shan Lai and Yi-Jin Chen, “FPGA Vernier Digital-to-Time Converter with 1.58ps Resolution and 59.3 Minutes Operation Range,” IEEE Transactions on Circuits and Systems I, Vol. 57, pp.1134-1142, 2010.

[27] “Stratix IV Device Handbook” available from the Altera Corporation, http://www.altera.com

[28] R.-J. Yang, S.,-P. Chen, S.-I. Liu, “A 3.125-Gb/s clock and data recovery circuit for the 10-Gbase-LX4 ethernet,” IEEE Journal of Solid-State Circuits, vol. 39, pp. 1356-1360, 2004.

[29] C.-K.K. Yang, R. Farjad-Rad, M.A. Horowitz, “A 0.5-μm CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling,” IEEE Journal of Solid-State Circuits, vol. 33, pp. 713-721, 1998.

[30] B.G. Goldberg, “The evolution and maturity of Fractional-N PLL synthesis,” Microwave Journal, vol. 39, pp. 124-134, 1996.

[31]M. Brownlee, P.K. Hanumolu, K. Mayaram, U.-K. Moon, “A 0.5-GHz to 2.5-GHz PLL with fully differential supply regulated tuning,” IEEE Journal of Solid-State Circuits, vol. 41, pp. 2720-2727, 2006.

[32] “Quartus II Handbook Version 9.1,” http://www.home.agilent.com/.

[33] M. Morris Mano, “Digital Design Third Edition,” Prentice Hall, 2002.

[34] “Quartus II Help v11.0,” http://quartushelp.altera.com/current/

[35] T.-H. Chao, Y.-C. Hsu, J.-M. Ho, D. K. Boese, B. A. Kahng, “Zero skew clock routing with minimum wirelength,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 39, pp. 799-814, 1992.

[36] F. D. Wann, A. M. Franklin, “Asynchronous and Clocked Control Structures for VSLI Based Interconnection Networks,” IEEE Transactions on Computers, vol. C-32, pp. 284-293, 1983.

[37] M.-B. Lin, “Digital System Design and Practices: Using Verilog HDL and FPGAs,” Wiley, 2008.

[38] “Agilent Technologies 81133A and 81134A 3.35 GHz Pulse Pattern Generators Data Sheet Version 1.2,” available from Agilent Corporation, http://www.home.agilent.com/.

[39] “Datasheet: Digital Phosphor Oscilloscopes and Digital Serial Analyzers,” available from Agilent Corporation, www2.tek.com/cmswpt/madetails.lotr?ct=MA&cs=mur&ci=14588&lc=EN.

[40] A.M. Amiri, A. Khouas, M. Boukadoum, “Pseudorandom stimuli generation for testing time-to-digital converters on an FPGA,” IEEE Trans. Instrum. Meas. vol. 58, pp. 2209-2215, 2009.

[41] “IEEE standard for terminology and test methods for analog-to-digital converters,” IEEE Std., 13 Jun. 2001.

[42]L. Arpin, M. Bergeron, M.-A. Tetrault, R. Lecomte, R. Fontaine, “A sub-nanosecond time interval detection system using FPGA embedded I/O resources,” IEEE Transactions on Nuclear Science, vol. 57, pp. 519-524, 2010.