快閃記憶體因其低功率消耗、高儲存密度以及存取速度快等優點被廣泛應用於固態硬碟、手機等消費性電子產品中。快閃記憶體是由浮閘電晶體所組成的非揮發性記憶體，快閃記憶體藉由改變浮閘電晶體中的電子數量來儲存資料。隨著製程的演進與多階儲存細胞技術的發展，快閃記憶體的儲存密度得以不斷的提高，但同時也使記憶體細胞的雜訊邊界縮小，導致記憶體可靠度與耐久性的降低。最常被用來解決這些問題的方案為錯誤更正碼技術，錯誤更正碼能有效處理快閃記憶體中主要的永久性故障與干擾性故障。然而快閃記憶體細胞隨著抹寫次數的增加，編碼字中的故障細胞數量也會逐漸地上升，當一個編碼字內的故障位元數量超過使用的錯誤更正碼技術的修正能力時，該編碼字就無法被修復。
因此，本篇論文提出適應性錯誤更正碼技術來解決這些問題，並結合過去研究中所提出的修正餘度 (Correction Slack) 概念，藉由錯誤更正碼的錯誤檢測能力來觀測編碼字的故障狀況，並計算錯誤更正碼剩餘的修復能力。本技術主要的概念為針對剩餘修正能力較低的特定記憶體頁，提高錯誤更正碼的修正能力以提供額外保護，一方面可維持記憶體的可靠度，同時其他剩餘修正能力較高的記憶體頁可避免使用高強度的錯誤更正碼造成的效能負擔。本研究也提出了更正利用率 (Correction Utilization) 的概念，以評估錯誤更正碼對記憶體效能的影響。
本研究中實現了適應性錯誤更正碼技術之電路，並於 64 MB 之快閃記憶體上進行了可靠度、硬體成本、修復率以及良率的分析。實驗結果顯示本篇技術可大幅減少錯誤更正碼資源的使用，並維持記憶體之及可靠度。相較於全面配置相同修正能力的錯誤更正碼技術減少了 84% 錯誤更正碼資源的使用，在正常操作下經過95,000小時後仍能維持 98.79% 之可靠度。

Due to the advantages of low power consumption, high storage density, and high performance, flash memory is widely used in consumer products such as solid-state disk (SSD) and mobile devices. Flash memory is a non-volatile storage device and consists of floating-gate transistor arrays. The flash memory cell represents data values by altering the amount of electrons stored in the floating gate transistor. With the advancement of fabrication technology and the number of bits can be stored in a cell such as the multi-level cell (MLC), the triple-level cell, and the quad-level cell (QLC), the storage density of flash memory is improved significantly. However, the noise margins of the flash memory cells become smaller. This may deteriorate the reliability and endurance of the memory. Error correction code (ECC) is one of the most widely used methods to cure these issues. ECC can effectively deal with the major fault models of flash memory, such as the permanent faults and the disturb faults. However, the number of faulty cells in a flash memory will increase greatly as the number of P/E cycles increases. When the number of the faulty bits exceeds the correction capability of adopted ECC, the codewords cannot be properly corrected.
Therefore, this thesis proposes progressive ECC technique to solve these problem. With the concept of correction slack from previous work, we can utilize the error detection capability of the adopted ECC to get the precise error information of the flash page, and calculate the correction slack, which means the remaining correction capability of ECC. Our technique focuses on the pages with lower correction slack and enhance the correction capability of ECC of these page to keep up the reliability of the memory. The other pages with higher correction slack can avoid the performance overhead from using strong ECC. We also introduce the concept of correction utilization to evaluate the performance overhead of adopted ECC.
The VLSI design of the proposed techniques and architectures are implemented. The reliability, repair rate, yield, and hardware overhead by using the proposed techniques on a 64 MB flash memory are analyzed and evaluated. According to experimental results, the proposed techniques can reduce the resource usage of the error correction code without heavily affecting the reliability of memory. As compared with merely applying ECC with the same correction capability to all data pages of the flash memory, the resource usage of ECC is reduced by 84%. Moreover, the reliability of a flash memory can remain 98.79% after 95,000 hours of normal operation.

[1] A. S. Spinelli, C. M. Compagnoni, A. L. Lacaita, "Reliability of NAND flash memories: Planar cells and emerging issues in 3D devices", Computers, vol. 6, no. 2, pp. 16, 2017, [online] Available: http://www.mdpi.com/2073-431X/6/2/16.
[2] Y. Li and K. N. Quader, “NAND flash memory: challenges and opportunities,” Computers, pp. 23-29, Aug. 2013.
[3] R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, “Introduction to flash memory,” Proc. IEEE, vol. 91, no. 4, pp. 489-502, Apr. 2003.
[4] R. C. Baumann, “Soft errors in advanced semiconductor devices—Part I: The three radiation sources” IEEE Trans. Device and Materials Reliability, vol. 1, no. 1, pp. 17-22, Mar. 2001.
[5] W. Kuo, W. T. K. Chien, and T. Kim, “Reliability, yield, and stress burn-in,” Kluwer Academic Publishers, Boston, 1998.
[6] C. S. Hou and J. F. Li, “Testing disturbance faults in various NAND flash memories,” in Proc. IEEE Asian Test Symp. (ATS), pp. 221-226, Nov. 2013.
[7] M. G. Mohammad and K. K. Saluja, “Flash memory disturbances: modeling and test,” in Proc. IEEE VLSI Test Symp. (VTS), pp. 218-224, Apr. 2001.
[8] Y. Y. Hsiao, C. H. Chen, and C. W. Wu, “A built-in self-repair scheme for NOR-type flash memory,” in Proc. IEEE VLSI Test Symp. (VTS), pp. 114-119, Apr. 2006.
[9] Y. Y. Hsiao, C. H. Chen, and C. W. Wu, “Built-in self-repair schemes for flash memory,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 8, pp. 1243-1256, Aug. 2010.
[10] O. Ginez, J. M. Portal, and H. Aziza, “Reliability issues in flash memories: an on-line diagnosis and repair scheme for word line drivers,” in Proc. Int’l Workshop on Mixed-Signals, Sensors, and Systems Test, pp. 1-6, June 2008.
[11] D. Frohman-Bentchkowsky, “FAMOS – A new semiconductor charge storage device,” Solid State Electron., vol. 17, pp. 517–520, 1974.
[12] M. Woods, “An E-PROM’s integrity starts with its cell structure,” in Nonvolatile Semiconductor Memories: Technologies, Design, and Application, C. Hu, Ed. New York: IEEE Press, 1991, Ch. 3, pp. 59–62.
[13] F. Masuoka, M. Momodomi, Y. Iwata, and R. Shirota, “New ultra high density EPROM and flash EEPROM with NAND structured cell,” IEEE Tech. Dig. IEDM, pp. 464-467, 1984.
[14] R. Bez, E. Camerlenghi, A. Modelli and A. Visconti, “Introduction to flash memory” Proc. IEEE, vol. 91, no. 4, pp. 489-502, Apr. 2003
[15] H. Kim and S. Ahn, “BPLRU: A buffer management scheme for improving random writes in flash storage,” In Proc. of FAST’08, 2008.
[16] S. Lin and D. J. Costello, Error control coding, 2nd ed., Englewood Cliffs, NJ: Pearson Prentice Hall, 2014.
[17] R. Micheloni, R. Ravasio, A. Marelli, E. Alice, V. Altieri, A. Bovino, L. Crippa, E. Di Martino, L. D’Onofrio, A. Gambardella, E. Grillea, G. Guerra, D. Kim, C. Missiroli, I. Motta, A. Prisco, G. Ragone, M. Romano, M. Sangalli, P. Sauro, M. Scotti, and S. Won, “A 4Gb 2b/cell NAND flash memory with embedded 5b BCH ECC for 36MB/s system read throughput,” in Proc. IEEE Int’1 Solid-State Cir. Conf. (ISSCC), pp. 497-506, Feb. 2006.
[18] X. Youzhi, “Implementation of Berlekamp-Massey algorithm without inversion,” IEE Proc. Communications, Speech and Vision, vol. 138, no. 3, pp. 138-140, June 1991.
[19] Y. Sugiyama, M. Kasahara, S. Hirasawa, and T. Namekawa, “A method for solving key equation for decoding Goppa codes,” Information and Control, pp. 87-99, Jan. 1975.
[20] S. Tanakamaru, Y. Yanagihara, and K. Takeuchi, “Error prediction LDPC and error recovery schemes for highly reliable Solid-State Drives (SSDs),” IEEE J. Solid-State Circuits, vol. 48, no. 11, pp. 2920-2933, Nov. 2013.
[21] T.-H. Chen, Y.-Y. Hsiao, Y.-Y. Hsiao, and C.-W. Wu, “An adaptive-rate error correction scheme for NAND flash memory,” 27th IEEE VLSI Test Symposium (VTS), pp. 53–58, 2009.
[22] Y. Hu, N. Xiao, and X. Liu, "An elastic error correction code technique for NAND flash-based consumer electronic devices," IEEE Trans. Consumer Electronics, vol. 59, no. 1, pp. 1-8, Feb. 2013.
[23] S. K. Lu, and W. C. Tsai, “Adaptive fault tolerant techniques for improving reliability of flash memory,” in Proc. IEEE Work. on RTL and High Level Test. (WRTLT), pp. 1-4, June 2018.
[24] T. S. Chung, D. J. Park, S. Park, D. H. Lee, S. W. Lee, and H. J. Song, “A survey of flash translation layer,” Journal of Systems Architecture, vol. 55, no. 5-6, pp. 332-343, May 2009.
[25] J. Kim, J. M. Kim, S. H. Noh, S. L. Min, and Y. Cho, “A space-efficient flash translation layer for Compact Flash systems,” IEEE Trans. Consumer Electronics, vol. 48, no. 2, pp. 366-375, May 2002.
[26] R. Subramani, H. Swapnil, N. Thakur, B. Radhakrishnan, and K. Puttaiah, “Garbage Collection Algorithms for NAND Flash Memory Devices -- An Overview,” in Proc. Modeling Symp. (EMS), pp. 81-86, Nov. 2013.
[27] M. C. Yang, Y. M. Chang, C. W. Tsao, P. C. Huang, Y. H. Chang and T. W. Kuo, "Garbage collection and wear leveling for flash memory: Past and future," in Proc. Int'l Conf. Smart Computing (SMARTCOMP), pp. 66-73, Nov. 2014.
[28] R. Dekker, F. Beenker, and L. Thijssen, "Fault modeling and test algorithm development for static random-access memories," in Proc. IEEE Int’l Test Conf., pp. 343-352, Sept. 1988.
[29] IEEE 1005 standard definitions and characterization of floating gate semiconductor arrays, Piscataway, NJ: IEEE Standards Dept., 1999.
[30] J. C. Yeh, K. L. Cheng, Y. F. Chou, and C. W. Wu, “Flash memory testing and built-in self-diagnosis with march-like test algorithms,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 6, pp. 1101-1113, June 2007.
[31] C. T. Huang, J. C. Yeh, Y. Y. Shih, R. F. Huang, and C. W. Wu, “On test and diagnostics of flash memories,” in Proc. IEEE Asian Test Symp. (ATS), pp. 260-265, Jan. 2005.
[32] S. Y. Kuo and W. K. Fuchs, “Efficient spare allocation in reconfigurable arrays,” IEEE Design and Test of Computers, vol. 4, no. 1, pp. 24-31, June 1987.
[33] C. T. Huang, C. F. Wu, J. F. Li, and C. W. Wu, “Built-in redundancy analysis for memory yield improvement,” IEEE Trans. Reliability, vol. 52, no. 4, pp. 386-399, Dec. 2003.
[34] T. Kawagoe, J. Ohtani, M. Niiro, T. Ooishi, M. Hamada, and H. Hidaka, “A built-in self-repair analyzer (CRESTA) for embedded DRAMs,” in Proc. Int’l Test Conf. (ITC), pp. 567-574, Oct. 2000.
[35] S. K. Lu, C. L. Yang, Y. C. Hsiao, and C. W. Wu, “Efficient BISR techniques for embedded memories considering cluster faults,” IEEE Trans. Very Large Scale Integr. Syst., vol. 18, no. 2, pp. 184-193, Feb. 2010.
[36] K. Pagiamtzis and A. Sheikholeslami, “Content-addressable memory (CAM) circuits and architectures: A tutorial and survey,” IEEE J. Solid-State Circuits, vol. 41, no. 3, pp. 712–727, Mar. 2006.
[37] R. F. Huang, J. F. Li, J. C. Yeh, and C. W. Wu, “A simulator for evaluating redundancy analysis algorithms of repairable embedded memories,” in Proc. IEEE Int’l Workshop Mem. Technol., Des. Testing (MTDT), pp. 68–73, July 2002.
[38] I. Koren and Z. Koren, “Defect tolerant VLSI circuits: techniques and yield analysis,” in Proc. IEEE, vol. 86, pp. 1817-1836, Sept. 1998.