數位脈衝寬度調變技術(Digital Pulse Width Modulation，DPWM)目前運用的範疇有電源管理IC應用、控制馬達轉速及LED驅動電路等，近來亦有文獻提出以DPWM概念實現D類音頻放大器等電路，故我們更期待未來DPWM之應用能更趨廣泛，以證明本論文所提出之DPWM的價值性。
在參閱目前各項DPWM相關文獻後，本論文主要目的將DPWM運用的範疇針對應用在D類音頻放大器電路上，並依據其操作頻率與解析度採取適合的設計規格，提出高精度數位脈衝寬度調變器，透過環形震盪器搭配計數器組成本論文之主要架構，使用此方式，可達到節省面積與成本，且又可進一步提高解析度，功耗卻不會等比例增加，以簡單架構獲取極佳效能。
採用環形震盪器搭配計數器組成本論文之主要電路，再利用輸入的數位值產生對應之責任週期(Duty Cycle)輸出，在解析度高達16位元時面積小，功耗低，以TSMC 0.18μm 1P6M製程實現電路，晶片核心電路面積0.047mm2，經過量測其操作頻率為252.3KHz時，功耗為9.23mW，INL介於-0.49∼+0.31LSB之間，更可證明其線性度表現極佳，此電路設計確實優於目前其他DPWM電路之設計，具有面積小、功耗低、高解析度皆為其優越特性。

The digital pulse width modulation (DPWM) has been widely applied to power management IC, motor speed controller, LED driver, and Class-D amplifier. In this thesis, we focus on the DPWM’s application of Class-D audio amplifier with excellent performance. To achieve high accuracy, the DPWM incorporates ring oscillator combined with counter for coarse duty adjustment and phase interpolation for fine duty tuning. The major advantages of the proposed structure are small chip size, low cost, high resolution and low power consumption.
The target resolution is set to 16-bits and the chip has been implemented in TSMC 0.18-μm Mixed-Signal 1P6M CMOS process with a core area of 0.047 mm2 only. The measured operation frequency is 252.3 KHz with a power consumption of 9.23 mW. The INL is -0.49 to +0.31 LSB which proves the superiority of the proposed circuit.

[1]Wei-Hsu Chang, Hung-Shou Nien, Chih-Hung Chen, “A Digital Boost
Converter to Drive White LEDs,” IEEE APEC Conf., pp.558-564, 2008.
[2]B.J. Patclla, A. Prodic, A. Zireger, D. Maksimovic, “High-Frequency Digital PWM Controller IC for DC-DC Converters, ” IEEE Transactions on Power Electronics., Vol. 18, No. 1., pp.438-446, Jan. 2003.
[3]X. Wang, X. Zhou, J. Park, and A. Q. Huang, “Design and implementation of a 9-bit 8 MHz DPWM with AMI06 process,” in Proc. IEEE APEC Conf., pp. 540-545, 2009.
[4]X.Wang, X. Zhou, J. Park, R. Guo and A. Q. Huang, “Analysis of Process-Dependent Maximal Switching Frequency, Choke Effect, and Its Relaxed Solution in High-Resolution DPWM,” IEEE Transactions on Power Electronics., Vol. 25, No. 1., pp.152-157, Jan. 2010.
[5]B. H. Gwee, J. S. Chang, and H. Li, “A micro-power low-distortion digital pulse width modulator for a digital class D amplifier,” IEEE Transactions on Circuits and Systems-II, Vol. 49, no. 4, pp.245, Apr. 2002.
[6]Grant, D.A. Darroman, Y. Burrow, S., “ Class-D amplification combined with switched-mode power conditioning-the route to long battery life,” IEEE, Vol. 48, Issue 3, pp.677-683, Aug. 2002.
[7]Streitenberger, M.; Felgenhauer, F. Bresch, H.; Mathis, W.,“Class-D audio amplifiers with separated base band for low-power mobile applications,” IEEE 26-28, pp.186-189, Jun. 2002.
[8]Kyu Min Cho; Won Seok Oh; Won Sup Chung; Hee Jun Kim, “A new class-D stereo audio amplifier using direct speaker current control,” IEEE, Vol. 2, 20-25 pp.1308-1310, Jun. 2004.
[9]Yasuda, A.; Kimura, T. Ochiai, K. Hamasaki, T., “A Class-D Amplifier Using a Spectrum Shaping Technique [audio power amplifier],” IEEE 3-6, pp.173-176, Oct. 2004.
[10]A. Syed, E. Ahmed, E. Alarcn, and D. Maksimovic, “Digital Pulse Width Modulator Architectures,” IEEE PESC., June. 2004.
[11]S. Bibian, and H. Jin, “High Performance Predictive Dead-beat Digital Controller for DC Power Supplies,” IEEE Trans. on Power Electron., vol.17, no. 3, pp. 420-427, May. 2002.
[12]A. Prodic, D. Maksimovic, and R. W. Erickson, “Digital Controller Chip Set for Isolated DC Power Supplies,” IEEE APEC Conf., pp. 866-872, 2003.
[13]W. Zhang, G. Feng, Y. Liu, and B. Wu, “A Digital Power Factor Correction (PFC) Control Strategy Optimized for DSP,” IEEE Trans. on Power Electronics, vol. 19, no. 6, pp. 1474-1485, Nov. 2004.
[14]X. Zhou, “Low-Voltage High-Efficiency Fast-Transient Voltage Regulator Module, ” VPI & SU Ph.D Thesis, 1999.
[15]William Shing Tak Yan and Howard Cam Luong, "A 900-MHz CMOS Low-Phase-Noise Voltage-Controlled Ring Oscillator", IEEE Transactions on Circuits and Systems-II:Analog and Digital Signal Processing, Vol.48, No. 2., Feb. 2001.
[16]Analysis and Design. 3rd ed., New York: McGraw Hill, 2003.Behzad Razavi , "Design of Analog CMOS Integrated Circuit,"
[17]Il-won Seo, Seoul(KR); Kyu-hyun Kim, Suwon(KR),“Digital Phase Interpolator for Contorlling Delay Time and Method Thereof,” United States Patent, US 6,525,584 B2, from Nov. 15, 2001 to Feb. 25, 2003.
[18]M. Morris Mano, “Digital Design Third Edition,” Prentice Hall, 2002.
[19]黃弘一、許智淵、曾暐盛、鄭國興、朱元華，“洋蔥波型產生器與使用洋蔥波型產生器的展頻時脈產生器”，中華民國智慧財產局, TW 201123733 A1, Jul. 2011.
[20]鄒昌廷、劉偉行、王晟瑋，“利用二位元數位比較器實現之8位元數位比較器”，2007 National Computer Symposium, Vol. 2, pp. 478-487, Dec. 2007.
[21]鐘志偉，具適應性過電流保護機制之多階D類音頻放大器，碩士論文，國 立雲林科技大學電子工程研究所，雲林，2009。
[22]蕭培墉、吳孟賢，Hspice 積體電路設計分析與模擬導論，台灣東華書局股份有限公司，台北，Jan. 2005.
[23]張智星，MATLAB 程式設計與應用，全華圖書股份有限公司，台北，Feb. 2000.
[24]S. Bae, H. Chi, Y. Sohn, H. Park, “A VCDL-Based 6-760-MHZ Dual-Loop DLL With Infinite Phase-Shift Capability and Adaptive-Bandwidth Scheme,” IEEE J. Solid-State Circuits, vol. 40, pp. 1119-1129, May. 2005.
[25]A. P. Dancy, A. P. Chandrakasan, “Ultra low power control circuits for PWM converters,” proceedings of the IEEE PESC, pp. 21-27, 1997.
[26]V. Yousefzadeh, T. Takayama, D. Maksimović, “Hybrid DPWM with Digital Delay-Locked Loop,” IEEE Workshop on Computers in PowerElectronics, COMPEL, 2006.
[27]A. V. Peterchev, J. Xiao, S. R. Sanders,“Architecture and IC Implementation of a Digital VRM Controller,” IEEE Tran. Power Electron., vol. 18, pp. 356-364, Jan. 2003.
[28]R. E. Foley, R. C. Kavanagh, W. P. Mamane and M. G. Egan, “An Area-Efficient Digital Pulse Width Modulation Architecture Suitable for FPGA Implementation,” APEC, vol. 3, pp. 1412-1418., 2005.
[29]A. Syed, E. Ahmed, D. Maksimovic, “ Digital PWM Controller with Feed-Forward Compensation,” IEEE APEC, pp. 60-66, 2004.
[30]Poki Chen, Tuo-Kuang Chen, Hsiao-Tzu Hu,Yu-Han Peng and Yi-Jin Chen, “A Digital Pulse Width Modulator Based on Pulse Shrinking Mechanism,” IEEE PEDS, No. 433, Nov. 2009.
[31]A. F. Rad. W. Dally, H. T. Ng, A. Senthinathan, M. J. E. Lee, R. Rathi. J. Poulton, “A Low-Power Multiplying DLL for Law-Jitter multi Gigahertz Clock Generation in Highly Integrated Digital Chips,” IEEE Journal of Solid-State Circuits, Vol. 37, No. 12, Dec. 2002.
[32]H. H. Chang, J. W. Lin, S. I. Liu. “A Fast Lacking and Low Jitter Delay-Locked Loop Using DHDL,” IEEE Journal of Solid-Stare Circuits., Vol. 38., No. 2, pp. 343, Feb. 2003.