快閃記憶體有著高密度、低成本與高可靠度等優點，使得消費性市場的需求量持續大幅成長。為了更加提高儲存密度與降低單位儲存成本，使得製程逐漸縮小，單位細胞的儲存資料量也逐漸提升，導致臨限電壓的間距愈來愈小，細胞與細胞之間的干擾也逐漸增加，導致可靠度與耐久度下降，為了解決這些問題，三維快閃記憶體被提出。由於存在製程變異，導致三維快閃記憶體的每一層之原始 位元錯誤率有所不同，在寫入清除次數於 10,000 時，將會有 6 倍多的差異，並且隨著寫入清除次數的增加與資料保存時間的增加，差異的倍數將持續擴大。而原始位元錯誤率的上升會造成資料發生錯誤的機率上升，為了解決這個問題，傳統上採用一致性保護，利用最差狀況來進行錯誤更正碼的保護，對於三維快閃記憶體來說，為了保護最差的層，會對其它較好的層造成額外的浪費，不但浪費儲存空間，更強的錯誤更正碼保護能力會帶來額外的編解碼時間與效能損耗，並產 生過多的硬體成本。

因此本篇論文提出適應性錯誤更正碼快取技術，利用三維快閃記憶體各層有著非常大的原始位元錯誤率差異，將各層群集成不同的層群組，並且配置對應強度的預設錯誤更正碼保護能力階級，能夠更加符合實際所需。另外隨著原始位元錯誤率的增加，本篇論文結合過去的研究所提出的修正餘度概念，能夠檢測編碼字是否需要額外的保護能力，提供適應性的錯誤更正碼保護能力階級，能夠提升三維快閃記憶體的可靠度與耐久度。另外結合過去的研究所提出的快取概念，將提升錯誤更正碼保護能力所產生額外檢查位元，儲存到額外的靜態隨機存取記憶體，在三維快閃記憶體斷電時，能夠寫回三維快閃記憶體做永久儲存，並且再次啟動時，能夠讀回靜態隨機存取記憶體做使用，也能避免對三維快閃記憶體產生額外的空間浪費，並且避免需要分別讀取編碼字與額外檢查位元，增加寫入讀取 次數，並且對效能造成影響。

本篇論文也開發可以模擬修復率的模擬器，並且對於有效良率、可靠度與硬體成本進行模擬與分析，並完成超大型積體電路的實現與佈局。從實驗結果可以 得知，本篇論文提出的方法與傳統上採用一致性保護方法在配置 20 位元錯誤更 正碼保護能力之下做比較，修復率能提升 20.05 %、有效良率能提升 2.58%、硬體成本能節省 47.01 %，並且可靠度可以在 1800000 小時維持在 0.999。

Flash memory has the advantages of high density, low cost and high reliability, which has caused the demand of the consumer market to continue to grow substantially. In order to further increase the storage density and reduce the unit storage cost, the manufacturing process is gradually scaled down, and the amount of stored data per unit cell is gradually increased. However, this results in a smaller and smaller threshold voltage margin, and the cell-to-cell interference is gradually increased and the reliability is also declining. In order to solve these problems, 3D flash memory has been proposed. Due to the process variations, the raw bit error rate of each layer in the 3D flash memory is different. There can be a difference of more than 6 times when the number of P/E cycles is 10,000. The differences might continue to expand with the number of P/E cycles and the increasing of the retention time. The worsened raw bit error rate will increase the probability of data errors. In order to solve this problem, traditionally, uniform protection is used. The protection of error correction code is based on the worst-case scenario. For the 3D flash memory, in order to protect the worst layers, additional resources will be wasted if the same protection capability is also applied for other less suffered layers.

Therefore, this thesis proposed adaptive error correction code (AEC) caching technique, using the fact that each layer of the 3D flash memory has a very large difference of raw bit error rate. AEC assigns each layer into a different layer group and configure a corresponding strength for the default error correction code level, which is more suitable with the real requirements. In addition, with the increase of the raw bit error rate, this paper combined with the concept of correction slack proposed by previous research, which can detect whether the codeword requires additional protection, provide adaptive error correction code level. This improves the reliability and durability of 3D flash memory. Combining with the caching concept proposed by the previous research, the extra check bits generated by the additional error correction code are stored in static random access memory. The extra check bits are be written back when the 3D flash memory is powered off and stores permanently. When the 3D flash memory is restarted, the extra check bits can be read back from the 3D flash memory to the static random access memory for use, and the extra storage space of the 3D flash memory can be avoided. Therefore, the need to read the codeword and extra check bits, which increases the number of writes and reads can be avoided.

This paper also developed a simulator that can simulate the repair rate, effective yield, reliability, and hardware overhead. We also completed the implementation and layout of very large integrated circuits. It can be seen from the experimental results that the method proposed in this paper is compared with the traditional uniform protection method under the protection capability of 20-bit error correction code. The repair rate can be increased by 20.05%, and the effective yield can be increased by 0.81%. The hardware cost can be saved by 47.01%, and the reliability can be maintained at 0.999 after 1800000 hours of operations.

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