研究生: |
鄭瑋徹 Wei-Che Cheng |
---|---|
論文名稱: |
多核心系統晶片測試流程最佳化之研究 A Study of Test Schedule Optimization for Multicore SoCs |
指導教授: |
陳維美
Wei-Mei Chen |
口試委員: |
林淵翔
Yuan-Hsiang Lin 林昌鴻 Chang-Hong Lin |
學位類別: |
碩士 Master |
系所名稱: |
電資學院 - 電子工程系 Department of Electronic and Computer Engineering |
論文出版年: | 2018 |
畢業學年度: | 106 |
語文別: | 中文 |
論文頁數: | 74 |
中文關鍵詞: | System on chip SoC test scheduling Dynamic voltage frequency scaling |
外文關鍵詞: | System on chip SoC test scheduling Dynamic voltage frequency scaling |
相關次數: | 點閱:569 下載:0 |
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隨著半導體製程的進步,積體電路的電路密度也逐年提升,且電路的開發也主要都偏往系統晶片去發展,往往一個嵌入式裝置就集結各式各樣的功能,像是各種手持裝置智慧型手機、平板等等,都是匯聚各式各樣的電路在一個裝置上,也因此提升了系統晶片測試的複雜度,也因為測試機台相當昂貴因此我們希望有效率的去測試我們的電路來達到降低成本的效果。
本論文研究半導體系統晶片測試時間縮短的辦法(TTR, test time reduction),目標最小化整體的測試時間(makespan),將產品上市之前對產品的各個項目進行測試,預先規劃好輸入輸出匯流排在將測試項目安排至機台來對產品進行評估。
本研究除了將我們的演算法套入單電壓系統晶片與過往的方法比較以外,也有為(DVFS, Dynamic Voltage Frequency Scaling)動態電壓頻率調整的系統晶片架構來進行比較,透過我們設計的基因演算法可以找出較短的測試排程,搭配不同的參數可以達到更好的效果,進而提升系統晶片的測試效率。實驗結果顯示我們的基因演算法不僅在DVFS架構下的SoC,排程出來的結果是優於貪婪演算法的,且在一般SoC d695、p22810和p93791中,d695在我們基因演算法得到的排程是皆優於過去的演算法,p22810及p93791則是大部分的排程結果都優於過去的演算法。
With the progress of semiconductor manufacturing, IP core’s density grew up year by year, and SoC design became more important. With the increase in the number of cores, testing SoC were more complicated. Lots of mobile devices tend to reduce power consumption because high power consumption would cause high temperature for device that consume battery’s lifetime. Many SoC designers employ dynamic voltage scaling and voltage islands that operate at multiple power supply voltage levels which could lower the power consumption but testing this kind of chip will increase cost on testing. SoC test scheduling is an important issue for testing the SoC (system-on-chip) which mainly effect the cost. We propose genetic algorithm to find an efficient scheduling to test SoC, our algorithm not only apply on normal 2D SoC to compare with other methods, we also can solve DVFS(Dynamic Voltage Frequency Scaling) SoC test scheduling. Experimental result on DVFS structure show our method obtaining the best result that effectively reduce test time. And result on itc02 benchmark is also better than other methods. Our makespan is shorter than other methods in most of circumstances so as to decrease SOC test cost.
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