以權重式元件面積配置為基礎來優化並實現關鍵比率之類比積體電路

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研究生：	周平利 Billion - Abraham
論文名稱：	以權重式元件面積配置為基礎來優化並實現關鍵比率之類比積體電路 The Optimization and Implementation of Weight-Based Device Area Allocation for Ratio-Critical Analog Integrated Circuit
指導教授：	陳伯奇 Poki Chen
口試委員:	黃育賢 Yuh-Shyan Hwang 陳建中 Jiann-Jong Chen 鍾勇輝 Yung-Hui Chung
學位類別：	碩士 Master
系所名稱：	電資學院 - 電子工程系 Department of Electronic and Computer Engineering
論文出版年：	2016
畢業學年度：	104
語文別：	英文
論文頁數：	94
中文關鍵詞：	元件面積配置、二進位權重電路、以INL為基礎之良率優化、積體電路、製程變異
外文關鍵詞：	Device area allocation, INL-based yield optimization, process variation, random mismatch
相關次數：	點閱：298 下載：8
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上一筆

隨著製程演進，電晶體的尺寸越縮越小，積體電路的效能受製程變異的影響越趨明顯。以最受認可的 Pelgrom 模型為例，元件面積越小所會遭遇的隨機誤配越大，將使晶片的效能劣化。設計者不能再專注於電路改善而已，佐以良好的佈局考量已是成功的不二法門。
先前有關元件佈局面積的研究雖有相當成效，但仍屬逐案討論的範疇，缺乏一般性的通則，常常讓工程師在面對未知的設計時感到無所適從。尤有甚者，該些論文皆只提供接近最佳種況的模擬而已，欠缺足夠的理論奧援，較難令人信服。為此，本論文將儘量提供精確的數學分析以支持我們所提出的元件面積優化配置，更將提出一般化的元件面積配置建議，讓工程師在面臨從未遇過的設計時能有所依循，減輕他們疑惑與負擔。相關的元件面積配置都以優化 INL 良率為目標。本論文將論及數種指標性類比電路關鍵元件的面積配置，相關的模擬與分析結果全然相符，測試元件的量測結果也證明本論文的面積配置建議確實優於以往。最後，我們也將試做一 10 位元 R-2R 架構之數位至類比轉換器，以展現本論文元件面積配置方法之優異性。

With device size shrinking of technology evolution, process variation becomes a very critical issue in designing integrated circuits (IC). According to Pelgrom’s model, the smaller device’s size, the larger random mismatch is and it makes the chip performance worse. Not only design, but also layout is very important nowadays for engineers to consider. Previously, the study of area allocation strategy was case-by-case only and did not propose general formulation to fully cover all design cases. Moreover, it was merely verified by selected simulations around the optimum. Mathematical calculation instead of theoretical analysis was made. However, the simulation results showed some discrepancies with the calculation. In this thesis, we would like to present not only theoretical study to cover all representative cases but also INL-based yield simulation to prove the excellence of the proposed weight-based area allocation strategy to ease the burden of all layout engineers. The results show that the calculation matches the simulation. Furthermore, a 10-bit R-2R digital-to-analog converter in a TSMC 0.18 μm standard process has been designed along with this area allocation strategy. Pre-simulation and post-simulation results prove that the mismatch is reduced significantly.

中文摘要	i
Abstract	ii
Table of Contents	iii
List of Figures	vi
List of Tables	ix
Chapter 1	1
Introduction	1
1.1	Motivation	1
1.2	Thesis Organization	4
Chapter 2	5
Process Variation and Area Allocation Strategy Overview	5
2.1	Process Variation	5
2.2	Mismatch	6
2.3	Pelgrom’s Model	9
2.4	Binary Weighted Circuit Area Allocation Strategy Overview	10
Chapter 3	15
Statistical Analysis and INL-Yield Simulation	15
3.1	Statistical Analysis of Process Variation	15
3.2	INL-Based Yield Optimization Overview	18
3.3	 Binary Weighted Circuits	20
3.3.1	Binary Weighted Circuits with Dummy	21
3.3.2	Binary Weighted Circuits without Dummy	25
3.4	 R-2R Ladder	28
3.4.1	Simple R-2R Ladder	29
3.4.2	Segmented R-2R Ladder	33
Chapter 4	40
Practical Implementation of R-2R Ladder Digital-to-Analog Circuit	40
4.1	Introduction	40
4.2	Design Implementation	41
4.2.1	R-2R Ladder (LSB part)	45
4.2.2	R Matrix (MSB Part)	47
4.2.3	4-bit Decoder	49
4.2.4	Differential Switch	49
4.2.5	Deglitcher	50
4.3	Layout Implementation	57
4.3.1	Decoder	57
4.3.2	Deglitcher	59
4.3.3	Differential NMOS Switches	59
4.3.4	R-2R Ladder (LSB part)	60
4.3.5	R Matrix (MSB Part)	62
Chapter 5	65
Simulation Results	65
5.1	Pre-Simulation	65
5.1.1	Current Consumption	66
5.1.2	INL/DNL (Monte Carlo Simulation)	68
5.1.3	Transient Response and SFDR	70
5.1.4	Corner Simulation	71
5.2	Post-Simulation	73
5.2.1	Current Consumption	73
5.2.2	INL/DNL	73
5.2.3	SFDR	76
5.3	Comparison with Other R-2R DAC	76
Chapter 6	77
Conclusion	77
References	78

                                

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