簡易檢索 / 詳目顯示

研究生: 羅君恆
Chun-heng Lo
論文名稱: 簡易匹配雙頻段15位元CMOS被動式UHF RFID標籤設計
A dual-band CMOS 15-bit passive UHF RFID Tag with an easily matched charge pump
指導教授: 姚嘉瑜
Chia-yu Yao
口試委員: 陳筱青
Hsiao-chin Chen
彭盛裕
Sheng-yu Peng
學位類別: 碩士
Master
系所名稱: 電資學院 - 電機工程系
Department of Electrical Engineering
論文出版年: 2014
畢業學年度: 102
語文別: 中文
論文頁數: 91
中文關鍵詞: 雙頻段被動式UHF RFID Tagenergy harvesting寬讀取功率範圍多級疊接式倍壓器
外文關鍵詞: dual-band passive UHF RFID tag, energy harvesting, wide input power range, easily matched charge pump
相關次數: 點閱:1657下載:0
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 本論文電路為雙頻段15位元CMOS被動式UHF RFID Tag,應用面鎖定於室內空間定位系統-倉儲管理。雙頻段為power link 925/866 MHz以及data link 433 MHz。本tag屬被動式,電源藉energy harvesting產生,而power link頻段負責傳送連續弦波訊號,經charge pump對電容充電以提供電源,此外power link頻段也供tag反散射ID時使用,至於data link頻段除了先乘載經reader編碼與調變的ID,還會再傳輸連續方波訊號,當作給tag所需之時脈使用。
    考量實際應用狀況;貨品上tag距離周遭reader或近或遠,因此本tag主要特色為寬讀取功率範圍。其中最高讀取功率上限,是藉著特殊設計的放電機制達成,其它特色如無穩壓器和無震盪器,首先取代穩壓器的是低功耗的二級limiter;其中第二級limiter輸入端可接受寬範圍電壓,並輸出穩定的電壓。至於取代震盪器是利用data link傳送tag所需的時脈訊號;當data link傳送完ID,繼續利用此頻段乘載連續方波訊號,envelope detector會將之解調成時脈訊號,供後方數位電路使用。另一特色是使用多級Dickson rectifier,經模擬與量測發現,級數較多的倍壓器較易和天線端做匹配;如此可減少使用SMD匹配元件,讓RF訊號能真正被tag吸收;進而拉長tag可被讀取距離。實際量測power link於925 MHz時,最低讀取功率為-23.02 dBm、最高讀取功率為18.7 dBm,而data link最低讀取功為-41.2 dBm、最高讀取功率為14.2 dBm。本論文利用台灣積體電路(TSMC) 0.18um mixed signal/RF 1P6M CMOS製程實現。


    This thesis presents a dual-band CMOS 15-bit passive UHF RFID tag chip. The tag is applied in the UHF RFID indoor localization system. Our design employs dual-band communication links that include the power link (925/866MHz) and the data link (433MHz). Because the tag is passive, the energy required by the tag is collected by energy harvesting. The power link uses continuous wave to charge the capacitance and backscatters the FM0-encoded ID. The data link transmits the OOK-modulated PIE-encoded ID to the tag first and provides the OOK-modulated square wave to the tag as the clock signal later.
    In the real application, the tag can be either far away or be close to the reader, so the tag has to be sensitive and sturdy enough to the wide input power range. Hence, the tag has been carefully designed especially for the case of high input power. Also, the tag employs two stages of limiters to replace the bandgap reference circuit. Another critical characteristic of the tag is that we use a multi-stage voltage doublers in the charge pump. This makes matching between the tag and the antenna relatively easy. The power link’s power range can achieve -23.02 dBm~ 18.7 dBm. The data link’s power range can achieve -41.2 dBm ~ 14.2 dBm. The proposed RFID tag is fabricated in TSMC 0.18um mixed signal/RF 1P6M CMOS process.

    摘要 I Abstract II 誌謝 III 目錄 IV 圖目錄 VII 表目錄 XII 第一章 緒論 1 1.1 簡介與背景 1 1.2 研究動機與目的 2 1.3 使用工具與模擬軟體 4 1.4 論文架構 4 第二章 RFID系統介紹 6 2.1 RFID系統使用頻段的選擇 6 2.2 RFID系統於空間定位的應用 7 2.3 RFID系統的通訊編碼與調變 9 2.3.1 ASK、FSK、PSK 9 2.3.2 OOK 11 2.3.3 PIE(Pulse-Interval Encoding) symbol編碼 12 2.3.4 FM0 symbol編碼 14 第三章 RFID Tag 電路設計 16 3.1 Tag 電路架構 16 3.2 Charge Pump、Stage-I Limiter and Power-on-reset 電路 18 3.2.1 Charge Pump 電路 18 3.2.2 Stage-I Limiter and Power-on-reset 電路 22 3.3 Envelope Detector 電路 24 3.4 PIE-to-Binary Decoder 電路 25 3.5 Baseband Processing Unit (BPU)電路 29 3.6 FM0 Encoder 32 3.7 Back-scatter 電路 33 3.8 Stage-II Limiter電路 35 第四章 模擬結果與晶片量測結果 40 4.1 Whole Chip Simulation Results I-Charging 40 4.1.1 The Lowest Input Power in Different Corners 42 4.1.2 The Medium Input Power in Different Corners 43 4.1.3 The Highest Input Power in Different Corners 45 4.2 Whole Chip Simulation Results II-Demodulation(Analog circuits→Post-Simulation、Digital circuit→Pre-simulation) 47 4.2.1 The Lowest Input Power in Different Corners 48 4.2.2 The Medium Input Power in Different Corners 50 4.2.3 The Highest Input Power in Different Corners 52 4.3 下線實作 54 4.3.1 設計流程 54 4.3.2 晶片佈局腳位介紹 55 4.4 晶片量測結果 57 4.4.1 PCB電路板製作 57 4.4.2 量測環境 58 4.4.3 量測考量 59 4.4.4 量測結果 60 4.5 與其它文獻比較 70 第五章 結論與未來展望 74 5.1 結論 74 5.2 未來展望 74 第六章 參考文獻 75

    [1] J. P. Curty, N. Joehl, C. Dehollain, and M. J. Declercq, “Remotely powered addressable UHF RFID integrated system”, IEEE J. Solid-State Circuits, vol. 40, pp. 2193-2202, Nov. 2005.
    [2]
    U. Karthaus and M. Fischer, “Fully Integrated passive UHF RFID transponder IC with 16.7μW minimum RF input power,” IEEE J. Solid-State Circuits, vol.38, pp. 1602–1608, Oct. 2003.
    [3]
    J. W. Lee and B. Lee “A long-range UHF-band passive RFID tag IC based on high-Q design approach,” IEEE Trans. Ind. Electron., vol. 56, pp. 2308–2316, July 2009.
    [4] M. Baghaei-Nejad, D. S. Mendoza, Z. Zou, S. Radiom, G. Gielen, L. R. Zheng, and H. Tenhunen, “A remote-powered RFID tag with 10Mb/s UWB uplink and -18.5dBm sensitivity UHF downlink in 0.18μm CMOS”, ISSCC Dig. Tech. Papers, Feb. 2009, pp. 198-200.
    [5] Radiom S., Baghaei-Nejad M., Mohammadpour-Aghdam K., Vandenbosch G., Zheng L., Gielen G., “Far-Field On-Chip Antennas Monolithically Integrated in a Wireless-Powered 5.8-GHz Downlink/UWB Uplink RFID Tag in 0.18-mu m Standard CMOS, ” in IEEE J. Solid-State Circuits,vol. 45, no. 9, pp. 1746-1758, 2010.
    [6] 柯宜欣,工作於UHF之高效率被動式CMOS RFID Tag。碩士論文,台灣科技大學,2011。
    [7] 李泳祿,雙頻段15位元CMOS被動式UHF RFID 標籤設計。碩士論文,台灣科技大學,2012。
    [8] 劉邦瑞,簡易匹配型倍壓器雙頻段15位元CMOS被動式UHF RFID標籤設計。碩士論文,台灣科技大學,2013。
    [9] 溫鈺柔,游標卡尺法時間至數位轉換器及其在室內RFID系統中距離量測上的應用。碩士論文,台灣科技大學,2012。
    [10] EPCTM Radio-Frequency Identity Protocols Class-1 Generation-2 UHF RFID Protocol for Communications at 860MHz-960MHz, Version 1.2.0.
    [11] D. M. Dobkin, The RF in RFID: Passive UHF RFID in Practice. Boston: Elsevier, 2007
    [12] Y. Jun, K. Wing-Hung, and T. Chi-Ying, “Analysis and Design Strategy of UHF Micro-Power CMOS Rectifiers for Micro-Sensor and RFID Applications, ” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, pp. 153-166, Jan. 2007.
    [13] S. R. Tiyyagura and S. Katare, “Low Power Voltage Reference Architectures,” in International Symposium on Signals, Circuits and Systems,2009.

    無法下載圖示 全文公開日期 2019/06/27 (校內網路)
    全文公開日期 本全文未授權公開 (校外網路)
    全文公開日期 本全文未授權公開 (國家圖書館:臺灣博碩士論文系統)
    QR CODE