由於鰭式場效電晶體(Fin Field Effect Transistors, FinFET)元件具有三面環繞閘極之設計結構，可以比傳統金屬氧化物半導體場效電晶體(Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET)元件有更強的閘極對通道之控制能力，因此可以抑制短通道效應(Short Channel Effects, SCEs)所造成之漏電流。雖然FinFET為三面環繞閘極元件，但隨著鰭片尺寸改變，每一面閘極對通道控制的能力也會發生變化，因此當尺寸增加，此時元件不全然是三閘極結構，有可能會構成三閘極與雙閘極所組成之元件結構，最終使得漏電流的途徑發生改變，因此必需仔細考量元件尺寸設計，要能同時兼顧元件高驅動電流與低漏電電流之特性。
本論文透過Synopsys TCAD對鰭式場效電晶體進行電性模擬分析，其中特別討論元件尺寸對奈米尺度電晶體特性之影響，並研究閘極長度小於10 nm之FinFET。研究表明，在閘極長度10 nm、鰭片寬度5 nm、鰭片高度30 nm之下，當汲極偏壓1V，且閘極偏壓1V時，可獲得導通電流18.4 µA；而在閘極偏壓0V時，漏電流為1.2 pA。

Because Fin Field Effect Transistors (FinFET) devices have a three-side gate design structure, it can provide more gate’s controllability than traditional Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) devices. Therefore, the leakage current which caused by short-channel effects (SCEs), FinFET has lower than MOSFET. Although the FinFET is a three-sided surround gate element, as the size of the fin changes, the ability of the gate on each side to control the channel will also change. Therefore, when the size increases, the device is not entirely a triple-gate structure and it may form a device structure composed of triple-gate and double-gate. Finally, the current path of leakage current would be changed. It is necessary to carefully consider the size of the device design and to consider the characteristics of high drive current and low leakage current of the device.
This thesis uses Synopsys TCAD to simulate a three-dimensional electrical simulation analysis of FinFET. The relationship between fin dimension size and leakage characteristics is the focus of the simulation and studies FinFET with gate lengths less than 10 nm. Studies have shown that when the gate length, fin width and fin height are set to 10 nm, 5 nm and 30 nm, respectively. When the drain bias voltage is 1V and the gate bias voltage is 1V, the on-current is 18.4 µA; moreover, when the bias voltage is 0V, the leakage current is 1.2 pA.

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