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研究生： 游家博
Chia-po Yu
論文名稱： 多輸入多輸出無線通訊系統之可調式結合偵測與解碼電路架構與實現
VLSI Architecture of Configurable Joint Detection and Decoding for MIMO Wireless Communication Systems
指導教授： 沈中安
Chung-An Shen
口試委員: 林昌鴻
Chang-Hong Lin
王煥宗
Huan-Chun Wang
學位類別： 碩士
Master
系所名稱： 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年： 2014
畢業學年度： 102
語文別： 中文
論文頁數： 84
中文關鍵詞： 多輸入多輸出 、積體電路設計 、偵測 、解碼 、樹狀搜尋
外文關鍵詞： Channel decoding, tree search, K-Best
相關次數： 點閱：723  下載：7 
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    • 多輸入與多輸出(MIMO)通訊技術已被廣泛認可為有效提高無線通訊系統傳輸通訊量及傳輸品質的方法，然而其接收器硬體複雜度過高的問題形成了巨大的挑戰。為了使MIMO接收器的複雜度降低至達成可實現性，並同時具有更高效能的傳輸通訊量及傳輸品質，本論文提出了一個新的演算法 – 可調式結合偵測與解碼(Configurable Joint Detection and Decoding, CJDD)及其硬體架構的設計與實現。與傳統遞迴分離式架構相比，CJDD架構將接收器端的偵測與解碼這兩個區塊做整合，使其成為單一區塊，進而達到降低位元錯誤率(BER)。另外，本論文提出的架構進一步使迴旋碼編碼器的編碼率(coded rate)與系統調變架構(modulation scheme)這兩個通訊系統中的主要參數，有著更多樣性的組合和可能性，進而可確實符合近代MIMO通訊系統(如LTE、LTE-A、802.11n/802.11ac等)的規範。因此，本論文所設計的硬體架構可同時支援(1)16QAM + 1/2RATE、(2)16QAM + 1/3RATE、(3)64QAM + 1/2RATE和(4)64QAM + 1/3RATE這四種組合。與傳統分離式架構相比，在位元錯誤率為10-5時，訊躁比(SNR)約分別降低1.5~6dB。本論文提出的架構經由TSMC 40-nm製程合成之後，最大操作頻率為833 MHz，平均生產量(throughput)為213.6 Mbps ~ 357.6 Mbps，架構面積為可等效成707.4 K個邏輯閘閘數，平均功率消耗為961.2 mW。

    Multi-Input Multi-Output (MIMO) wireless communication system has been widely recognized as a means of increasing data rates as well as improving transmission quality. However, the advantages provided through MIMO communications come along with prominent drawbacks of enormous system complexity. In order to reduce the complexity of MIMO receiver while still maintaining high data rate and low Bit Error Rate, this thesis presents the design and implementation of a novel architecture of Configurable Joint Detection and Decoding (CJDD). Compared with the conventional separate Detection and Decoding (SDD) scheme, the proposed CJDD architecture integrates the MIMO detector unit and Channel Decoder module into a single block such that a significantly improved BER can be ahievied with comparable hardware complexity. Moreover, the CJDD architecture proposed in this thesis can be operating under various combinations of system configurations as as code rates as well as modulation schemes. Therefore, the CJDD system can be deployed fullfilling the requirements of modern MIMO communication system like LTE, LTE-A, and 802.11n/802.11ac. Specifically, the CJDD engine is designed to support (1) 16QAM + 1/2RATE, (2) 16QAM + 1/3RATE, (3) 64QAM + 1/2RATE, and (4) 64QAM + 1/3RATE. Compared with separate Detection and Decoding, the required signal to noise ratio (SNR) can be reduced about 1.5 ~ 6 dB targeting at a BER of 10-5. In addition, the proposed design was synthesized with TSMC 40nm CMOS technology at 833-MHz clock frequency. An average throughput of 213.6 Mbps ~ 357.6 Mbps with area equivalent to 707.4 Kgates can be achieved.

    摘要 I Abstract II 誌謝 III 目錄 IV 圖目錄 VI 表目錄 VIII 第一章 序論 1 1.1 研究動機 1 1.2 研究方向 1 1.3 論文架構 2 第二章 系統架構及文獻探討 4 2.1 MIMO系統模型 4 2.2 MIMO接收器架構 6 2.2.1 前置處理器(Preprocessor) 7 2.2.2 樹狀搜尋引擎(Tree-Searching Engine) 9 2.2.3 通道解碼器(Channel Decoder) 10 第三章 可調式結合偵測與解碼演算法(CJDD) 12 3.1 傳統遞迴分離式架構(SDD)與結合式架構(JDD)的比較 12 3.2 結合式架構(JDD)演算法的限制 13 3.2.1 使用迴旋碼編碼器的結合式架構 14 3.2.2 編碼率與調變技術的組合限制 16 3.3 可調式結合偵測與解碼演算法(CJDD) 17 第四章 硬體架構設計 23 4.1 整體架構說明 24 4.2 細部架構說明 27 4.2.1 有效訊號點尋找器(VSF) 27 4.2.2 路徑長計算(PM) 36 4.2.3 排序器(Sorter) 45 第五章 實驗結果與效能分析 51 5.1 基於MATLAB實驗平台的效能模擬 53 5.1.1 SDD、JDD和CJDD的BER比較 53 5.1.2 不同區塊大小與不同K值的BER比較 55 5.2 基於FPGA的硬體驗證與實驗結果 59 5.3 晶片實現 60 5.3.1 效能分析 61 第六章 結論 69 參考文獻 70

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