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研究生: 游甘玉
GAN-YU YOU
論文名稱: 以塊體矽基板形成之垂直式功率金氧半場效電晶體
Vertical Power MOSFET Formed With Bulk Si Substrate
指導教授: 莊敏宏
Miin-Horng Juang
口試委員: 張勝良
Sheng-Lyang Jang
徐世祥
Shih-Hsiang Hsu
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2022
畢業學年度: 110
語文別: 英文
論文頁數: 56
中文關鍵詞: 傳統溝槽式功率金氧半場效電晶體垂直式功率金氧半場效電晶體溝槽式閘極
外文關鍵詞: Conventional trench power MOSFET, Vertical power MOSFET, Trench gate
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隨著5G世代快速的發展和對於節能的重視,許多的事物逐漸邁向自動化,使得功率積體電路的應用逐漸廣泛。功率金氧半場效電晶體具有元件尺寸小、低導通電阻值、高切換速度以及可承受大電壓及大電流等優點。
現在市面上多是採用垂直結構,傳統的垂直結構是採用磊晶片且接觸孔位於下方,這樣的結構是最佳的,但是,此結構與CMOS整合在一起會有困難。
為了整合問題,一般採用橫向結構,但是橫向結構的特性比較差且元件密度不高,所以此研究使用塊體矽基板來形成垂直式功率金氧半場效電晶體,以解決垂直結構與CMOS整合問題以及橫向結構特性不佳的問題。
此研究使用Sentaurus TCAD元件模擬軟體進行模擬分析,模擬結果顯示在相同的崩潰電壓下,垂直式功率金氧半場效電晶體的單位胞元電阻比傳統溝槽式功率金氧半場效電晶體低1.26倍。在相同的摻雜濃度和汲極偏壓下,垂直式功率金氧半場效電晶體的電場分布比傳統溝槽式功率金氧半場效電晶體低。
此研究也探討不同尺寸對垂直式功率金氧半場效電晶體特性的影響,發現漂移區長度為2.0 μm,主動區寬度為1.4 μm時擁有最低的單位胞元電阻,為最佳的元件尺寸。


With the development of the 5G generation rapidly and the emphasis on energy saving, many things are gradually moving towards automation, making the application of power integrated circuits gradually wider. Power MOSFET has a small device size, low on resistance, high switching speed, and the capability to sustain high breakdown voltage and high operating current [1]. Nowadays, the modern fabrication process basically uses a vertical structure. The conventional trench power MOSFET is uses an epi-wafer, and it’s the bottom drain contact. This structure is the best, but it is difficult to integrate with the CMOS.
In order to resolve the integration problem, the lateral power MOSFET is used instead. However, the lateral power MOSFET shows poor characteristics and low device density. Therefore, this study employs bulk silicon substrate to form the vertical power MOSFET, for CMOS integration and device performance. The Sentaurus TCAD simulation and device analysis are carried out [2]. The simulation results show that the unit cell specific on resistance of the vertical power MOSFET is 1.26 times lower than the conventional trench power MOSFET at the same breakdown voltage. This is because in the same drift region doping concentration and the drain bias voltage, the vertical power MOSFET can result in smaller electric field than the conventional trench power MOSFET.
The effects of different sizes on the characteristics of vertical power MOSFET are also studied. It is found that the device, with the drift region length of 2.0 μm and the active region width of 1.4 μm, would show optimal unit cell specific on resistance.

摘要 i Abstract ii Acknowledgment iii Contents iv List of Figures vi List of Tables viii Chapter 1 Introduction 1 1-1 Motivation 1 1-2 Conventional trench power MOSFET 2 1-3 Vertical power MOSFET 3 1-4 Device physical mechanisms 4 1-4-1 Avalanche breakdown 4 1-4-2 Punch-through breakdown 4 1-4-2 Tunneling breakdown 5 1-4-3 Latch-up 5 1-5 Thesis organization 5 Chapter 2 Device fabrication 6 2-1 Conventional trench power MOSFET 6 2-2 Vertical power MOSFET 9 Chapter 3 Results and discussion 13 3-1 Conventional trench power MOSFET with different active region width 13 3-2 Vertical power MOSFET with different active region width, at drift region length 1.8 μm and drain width 0.1 μm 16 3-3 Vertical power MOSFET with different active region width, at drift region length 1.8 μm and drain width 0.41 μm 19 3-4 Vertical power MOSFET with different drift region length 22 3-5 Vertical power MOSFET with different active region width 25 3-6 Vertical power MOSFET with different drift region doping concentration 28 3-7 Vertical power MOSFET with p- plate and different p- plate doping concentration 31 3-8 Vertical power MOSFET with p- plate and different drift region doping concentration 34 3-9 Comparison of conventional trench power MOSFET and vertical power MOSFET with same breakdown voltage 37 Chapter 4 Conclusion 41 References 42

[1] Y. Chen, X. Cheng, Y. Liu, Y. Fu, T. X. Wu, and Z. J. Shen, "Modeling and Analysis of Metal Interconnect Resistance of Power MOSFETs with Ultra Low On-Resistance," IEEE International Symposium on Power Semiconductor Device and IC’s, 2006, pp. 1-4.
[2] HW. Karner, C. Kernstock, Z. Stanojevic, O. Baumgartner, F. Schanovsky, and M. Karner, "TCAD-Based Characterization of Logic Cells: Power, Performance, Area, and Variability," International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2017, pp. 1-2.
[3] Riyaz Abdul Khadar, Chao Liu, Reza Soleimanzadeh, and Elison Matioli, "Fully Vertical GaN-On-Si power MOSFETs," IEEE Electron Device Letters, vol. 40, issue. 3, 2019, pp. 443-445.
[4] Tsuneo Ogura, "Recent Technical Trends and Future Prospects of IGBTs and Power MOSFETs, " International Power Electronics Conference (IPEC-Hiroshima 2014-ECCE ASIA), 2014, pp. 2068-2073.
[5] Masahiro Watanabe, "TCAD simulation of trench-gate IGBTs for prediction of carrier lifetime requirements for future scaled devices," IEEE 14th International Conference on ASIC (ASICON), 2021, pp. 1-4.
[6] Mitsuo Okamoto, Atsushi Yao, Hiroshi Sato, and Shinsuke Harada, "First Demonstration of a Monolithic SiC Power IC Integrating a Vertical MOSFET with a CMOS Gate Buffer," IEEE Transactions on Power Electronics, 2021, pp. 71-74.
[7] Matthew Barlow, Shamim Ahmed, A. Matt Francis, and H. Alan Mantooth, "An Integrated SiC CMOS Gate Driver for Power Module Integration," IEEE Transactions on Power Electronics, vol. 34, no. 11, 2019, pp. 11191-11197.
[8] K. Eikyu, A. Sakai, and T. Yamashita, "Multi-trench-gate Cell Concept for Low Voltage Super Junction Power MOSFETs," 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2020, pp. 553-556.
[9] Nick X. Sun and Alex Q. Huang, "An 0.35μm, 6mΩ, 43μΩ-cm2 Lateral Power MOSFET for Low- Voltage, Megahertz Switching Power Applications," IEEE Electron Device Letters, vol. 20, no. 7, 1999, pp. 351-353.
[10] Moufu Kong, Cong Liu, Hanzhi Chen, and Bo Yi, Xingbi Chen, "A Novel Low Channel Resistance LDMOS with Planar and Trench Gates," IEEE International Conference on Integrated Circuits, Technologies and Applications, 2019, pp. 119-120.
[11] Sola Woo and Sangsig Kim, "Covered source-channel tunnel field-effect transistors with trench gate structures," IEEE Transactions on Nanotechnology, vol. 18, 2018, pp. 1-5.
[12] Richard K. Williams, Mohamed N. Darwish, Richard A. Blanchard, Ralf Siemieniec, Phil Rutter, and Yusuke Kawaguchi, "The Trench Power MOSFET: Part I—History, Technology, and Prospects," IEEE Transactions on Electron Devices, vol. 64, issue. 3, 2017, pp. 674-687.
[13] Raghvendra Sahai Saxena and M. Jagadesh Kumar, "Trench Gate Power MOSFET: Recent Advances and Innovations," Advances in Microelectronics and Photonics, (Ed., S. Jit), Chapter 1, Nova Science Publishers, Inc. 400 Oser Avenue, Suite 1600, Hauppauge, NY 11788, USA, 2012, pp. 1-23.
[14] Jin Wei, Yuru Wang, Meng Zhang, Huaping Jiang, and Kevin J. Chen, "High-Speed Power MOSFET with Low Reverse Transfer Capacitance Using a Trench/Planar Gate Architecture," 29th International Symposium on Power Semiconductor Device and IC’s (ISPSD), 2017, pp. 331-334.
[15] Zheng Chen, Dushan Boroyevich, and Rolando Burgos, "Experimental Parametric Study of the Parasitic Inductance Influence on MOSFET Switching Characteristics," The 2010 International Power Electronics Conference - ECCE ASIA, 2010, pp. 164-169.
[16] Hoon Cho, Pawan Kapur, Pranav Kalavade, and Krishna C. Saraswat, "A Low Power, Highly Scalable, Vertical Double Gate MOSFET Using Novel Processes," 65th Annual Device Research Conference, 2007, pp. 173-174.
[17] Cyril Buttay, Tarek Ben Salah, Dominique Bergogne, Bruno Allard, Hervé Morel, and Jean-Pierre Chante, "Avalanche Behavior of Low-Voltage Power MOSFETs," IEEE Power Electronics Letters, vol. 2, issue. 3, 2014, pp. 104-107.
[18] Omar Saif, Afrina Hasan, "An Extended Model for a Punch Through (PT) Trench Insulated Gate Bipolar Transistor (IGBT) and Its Transient Characteristics," IEEE Region 10 Symposium (TENSYMP), 2020, pp. 427-430.
[19] Y. C. Ong, D. S. Ang#, K. L. Pey, S. J. O’Shea, K. Kakushima, T. Kawanago, H. Iwai, C. H. Tung, "Real-time observation of trap generation by scanning tunneling microscopy and the correlation to high-κ gate stack breakdown," IEEE International Reliability Physics Symposium, 2009, pp. 704-707.
[20] Baoxing Duan, Licheng Sun and Yintang Yang, "Analysis of the novel Snapback-Free LIGBT with fast-switching and improved latch-up immunity by TCAD Simulation," IEEE Electron Device Letters, vol. 40, issue. 1, 2019, pp. 1-3.

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