鎖相迴路（PLL: Phase-locked loops）是一種利用反饋（Feedback）控制原理
實現的頻率及相位的同步技術，鎖相迴路在眾多領域有應用，如無線通信、數位
電視、廣播等。在無線通信系統中，PLL 的特性非常重要，PLL 迴路依序為相位
偵測器(PFD)、充電幫浦(CP)、迴路濾波器(LF)、壓控振盪器(VCO)、除頻器(FD)，
最後再回到相位偵測器(PFD)完成一個完整迴路，PLL 組成子電路中又以壓控振
盪器和注入鎖定除頻器特性最重要，而本論文主要研究鎖相迴路之注入鎖定除頻
器設計。
首先，我們設計一個高性能寬頻除二注入鎖定除頻器（ILFD）。此除頻器使
用台積電0.18 μm 1P6M CMOS，晶片面積為0.896 × 0.906 mm2. 此 ILFD 使用互
感耦合兩個諧振頻率，它由兩個子ILFD 透過互感耦合組成。ILFD 可以在三種
鎖頻模式下運行。最佳的偏壓範圍條件產生較寬的鎖定範圍、低功耗和高品質
效能因數。在 1.83 mW 的功耗和0 dBm 的輸入功率下，鎖定範圍從2.3 至5.6
GHz 為3.3 GHz。最高的 FOM 可以達到46. 此 ILFD 可以有兩個非重疊的鎖定
範圍或重疊的鎖定範圍，這表明ILFD 使用雙諧振諧振器。當兩組除二注入鎖
定除頻器皆打開時，可以在低頻輸出端看見低頻和高頻鎖定範圍的重疊，因此設
計的 ILFD 鎖定範圍可以達到1.6〜10 GHz（144.83％）。
接著，第二部分提出了一種新的並發振盪注入鎖定分頻器（ILFD）。此設計
ILFD 由三組電容交叉耦合的子ILFD 組成，分別操作在1.85 ,4.73 和5.74 GHz。
兩個子 ILFD 通過一對MIM 電容耦合，採用TSMC 0.18 μmBiCMOS 技術實現，
晶片面積為1.2 × 1.196 mm2。通過控制開關電晶體的閘極電壓，ILFD 具有三
種不同的工作模式，高頻主導模式，低頻主導模式和並發振盪模式。此 ILFD 可
以在1.592 mW 的低功率下運行。在 VbiasL = 0.55V 時，在外部注入強度為0
dBm 時，可提供1.9 至5.8 GHz （101.29％）的低頻鎖定範圍，最大效能因數
（FOM）為63.63。
最後，第三部分一個新的合流三頻段除二注入鎖定除頻器（ILFD）使用台積
電0.18 μm 1P6M CMOS 製程來實現，晶片面積為1.04 × 1.14 mm2。此ILFD 由
三個頻段分別為1.52, 4.23 和5.86 GHz 的電容交叉耦合ILFD 組成。三組ILFD
由兩個互感耦合。通過控制開關電晶體的閘極電壓，ILFD 具有三種不同的工作
模式，高頻主導模式，低頻主導模式和並發振盪模式。在並發模式下，ILFD 可
以產生5.67 GHz，4.09 GHz 和1.51 GHz 的三種不同信號及諧波和交互調變。此
除頻器最佳除頻範圍工作電壓操作在0.7 伏特，整體功耗為8.89mW，在注入強
度為0 dBm 時，除頻範圍可從1.4 GHz ~ 5.1 GHz，百分比為113.85 %，控制偏
壓下最高FOM 可達52.94。

Phase-locked loops (PLLs) are frequency and phase synchronization techniques
implemented using feedback control principles. Phase-locked loops have applications in many fields, such as wireless communications, digital television, and broadcast. In the wireless communication system, PLL are very important, PLL components include Phase Frequency Detector (PFD), Charge Pump (CP), Loop Filter (LF), Voltage Controlled Oscillator (VCO), and Frequency Divider (FD). This thesis presents the design of Injection-Locked Frequency Dividers (ILFDs).

First, a high-performance wide-band divide-by-2 injection-locked frequency
divider (ILFD) in the 0.18 μm CMOS process is presented. The die area is 0.896 ×
0.906 mm2.The ILFD uses transformer-coupled resonator with two resonant
frequencies based on the lumped inductor model, and it consists of two sub-ILFDs
coupled by inductive coupling. The ILFD can operate in three modes with overlapped locking ranges.
The optimal bias condition yields wide locking range at low power with
high figure of merit. At the power consumption of 1.83 mW and at the input power of 0 dBm, the locking range is 3.3 GHz from 2.3 to 5.6 GHz. The highest FOM can reach 46. The ILFD can have two non-overlapped locking ranges or an overlapped locking range, this indicates the ILFD uses a dual-resonance resonator. When two sets of twoinjection-locking frequency dividers are turned on, the low-frequency and highfrequency range overlap can be seen at the low-frequency output buffer, the range can reach 1.6~10 GHz (144.83%).

Secondly, a new concurrent oscillating injection-locked frequency divider (ILFD)
is presented. The ILFD consists of three capacitive cross-coupled sub-ILFDs operating at 1.85, 4.73 and 5.74 GHz respectively. The two sub-ILFDs are coupled by a pair of MIM capacitors. The proposed ILFD has been implemented with the TSMC 0.18 μm BiCMOS technology. The die area of the concurrent oscillating ILFD is 1.2×1.196 mm2. By controlling the gate voltages of the switching transistors, the ILFD has three different operational modes; high-band dominant mode, low-band dominant mode and concurrent oscillation mode. The ILFD can operate at low power 1.592 mW. At VbiasL=0.55V, an external injected signal power Pinj of 0 dBm provides a low-band locking range from 1.9 to 5.8 GHz (101.29%) and the maximum figure of merit (FOM) is 63.63.

Finally, a new concurrent oscillating injection-locked frequency divider (ILFD) is presented. The ILFD consists of three capacitive cross-coupled sub-ILFDs operating at 1.52, 4.23 and 5.86 GHz respectively. The three sub-ILFDs are coupled by two transformers. The proposed ILFD has been implemented with the TSMC 0.18 μm CMOS technology. The die area of the concurrent oscillating ILFD is 1.04×1.14 mm2. By controlling the gate voltages of the switching transistors, the ILFD has three different operational modes; high-band dominant mode, low-band dominant mode and concurrent oscillation mode. In the concurrent mode, the free-running ILFD can generate differential signals at 5.67 GHz, 4.09 GHz and 1.51GHz, their harmonics and other cross-modulation products. The operating supply voltage is 0.7 volt and locking range is from 2.2~4.2 GHz (62.5%) at injection power Pinj = 0 dBm. The power consumption of the ILFD core is 1.19 mW. The highest FOM can reach 52.52.

[1] B. Razavi, “RF Microelectronics”, Upper Saddle River, NJ: Prentice Hall, 1998
[2] N. M. Nguyen and R. G. Meyer, “Start-up and frequency stability in highfrequency
oscillators,” IEEE J. Solid-State Circuit, vol. 27, no. 5, pp. 810–820,
May 1992.
[3] S. Smith, Microelectronic Circuit 4th edition, Oxford University Press 1998.
[4] B. Razavi, Design of Analog CMOS Integrated Crcuits, MC Graw Hall, 2001.
[5] P. Andreani, S. Mattisson, “On the use of MOS varactors in RF VCOs,” IEEE Journal
of Solid-State Circuits, vol. 35, no. 6, pp. 905-910, June 2000.
[6] B. Razavi, Design of Analog CMOS Integrated Circuits, Mc Graw Hill, 2001.
[7] Y. K. Koutsoyannopoulos, and Y. Papananos, “Systematic analysis and modeling
of integrated inductors and transformers in RF IC design,” IEEE Trans. Crcuits
and System-II, vol. 47, no. 8, pp. 699-713, 2000.
[8] A. Zolfaghari, A. Chan, and B. Razavi, “Stacked inductors and transformers in
CMOS technology,” IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 620-628, 2001.
[9] H. M. Greenhouse, “Design of planar rectangular microelectronic inductors,”
IEEE Transactions on Parts, Hybrids, and Packaging, vol. 10, pp. 101-109, Jun
1974.
[10] A. Hajimiri and T. H. Lee, “A general theory of phase noise in electrical
oscillators,” IEEE J. Solid-State Circuits, vol. 33, no. 2, pp. 179−194, Feb. 1998.
[11] J. J. Rael and A. A. Abidi, “Physical processes of phase noise in differential LC
Oscillators,” IEEE Custom Integrated Circuits Conference, 2000, pp. 569−572.
[12] T. Lee and A. Hajimiri, “Oscillator phase noise: a tutorial,” IEEE J. Solid-State
Circuits, vol. 35, no. 3, pp. 326−336, Mar. 2000.
[13] B. Razavi, Design of Analog CMOS Integrated Circuits, Mc Graw Hill, 2001.
[14] T. H. Lee, The Design of CMOS Radio Frequency Integrated Circuits, Cambridge
University Press 1998.
[15] D. Hauspie, E.-C. Park, and J. Craninckx, “Wide-band VCO with simultaneous
switching of frequency band, active core, and varactor size,” IEEE J. Solid-State
Circuits, vol. 42, no. 7, pp. 1472–1480, Jul. 2007.
[16] J. Craninckx and M. S. J. Steyaert, “A 1.75-GHz/3-V dual-modulus divide-by-
128/ 129 prescaler in 0.7 um CMOS,” IEEE J. Solid-State Circuits, vol. 31, pp.
890-897, July 1996.
[17] J. Craninckx and M. S. J. Steyaert, “A 1.75-GHz/3-V dual-modulus divide-by-128/
129 prescaler in 0.7μm CMOS,” IEEE J. Solid-State Circuits, vol. 31, pp. 890-
897, July 1996.
[18] Q. Huang and R. Rogenmoser, “Speed optimization of edge-triggered CMOS
circuits for gigahertz single-phase clocks,” IEEE J. Solid-State Circuits, vol. 31,
pp. 456-463, Mar. 1996.
[19] J. Lee and B. Razavi, “A 40 GHz frequency divider in 0.18μm CMOS technology,”
IEEE J. Solid-State Circuits, vol. 39, pp. 594-601, Apr. 2004.
[20] H. R. Rategh, and T.H. Lee, “Superharmonic injection-locked frequency dividers,”
IEEE J. Solid-State Circuits, vol. 34, pp. 813-821, June 1999.
[21] H. D. Wohlmuth and D. Kehrer, “A high sensitivity static 2:1 frequency divider up
to 27 GHz in 120 nm CMOS,” IEEE European Solid State Circuits Conference
(ESSCIRC), pp. 823-826, Sept. 2002.
[22] M. Tiebout, “A 480 uW 2 GHz ultra low power dual-modulus prescaler in 0.25 um
standard CMOS,” IEEE International Symposium on Circuit and System (ISCAS),
vol. 5, pp. 741-744, May 2000.
[23] H. Wu, and A. Hajimiri, “A 19 GHz 0.5 mW 0.35 μm CMOS frequency divider
with shunt-peaking locking-range enhancement,” IEEE ISSCC Dig. Tech. Papers,
pp. 412-413, Feb. 2001.
[24] R. J. Betancourt-Zamora, S. Verma, and T. H. Lee, “1 GHz and 2.8 GHz CMOS
injection- locked ring oscillator prescalers,” IEEE Symposium on VLSI Circuits,
pp. 47-50, June 2001.
[25] P. Kinget, R. Melville, D. Long, and V. Gopinathan, “An Injection Locking
Scheme for Precision Quadrature Generation,” IEEE J. Solid-State Circuits, vol.
37, pp. 845-851, July 2002.
[26] H. R. Rategh, and T.H. Lee, “Superharmonic injection-locked frequency dividers,”
IEEE J. Solid-State Circuits, vol. 34, pp. 813-821, June 1999.
[27] W. Z. Chen, and C. L. Kuo, “18 GHz and 7 GHz superharmonic injection-locked
dividers in 0.25pm CMOS technology,” IEEE European Solid State Circuits
Conference (ESSCIRC), pp. 89-92, Sept. 2002.
[28] H. Wu, “Signal generation and processing in high-frequency/high-speed silicon
based integrated circuits,” PhD thesis, California Institute of Technology, 2003.
[29] R. Adler, “A study of locking phenomena in oscillators,” Proc. IEEE, vol. 61,
pp.1380-1385, Oct. 1973.
[30] C.-W. Chang, S.-L. Jang, C.-W. Huang, and C.-C. Shin, “Dual resonance LC-tank
frequency divider implemented with switched varactor bias,” in Proc. IEEE Int.
Symp. VLSI Design, Autom. Test, Apr. 2011, pp. 1–4.
[31] S.-L. Jang, R.-K. Yang, C.-W. Chang, M.-H. Juang, and C.-C. Liu, ” Dual-band
transformer-coupled quadrature injection-Locked frequency dividers,” Microw.
Opt. Technol. Lett. , pp.1561-1564, July, 2011.
[32] S.-L. Jang, C.-W. Chang, J.-Y. Wun, and M.-H. Juang, ” Quadrature injectionlocked
frequency dividers using dual-resonance resonator,” IEEE Microw.
Wireless Compon. Lett., vol. 21, no. 1, pp. 37-39, Jan. 2011.
[33] N. Mahalingam, K. Ma, K. S. Yeo, and W. M. Lim, “Coupled dual LC tanks based
ILFD with low injection power and compact size,” IEEE Microw. Wireless
Compon. Lett., vol. 24, no. 2, pp. 105–107, Feb. 2014.
[34] S.-L. Jang, X.-Y. Hang, and W.–T. Liu, ”Review: capacitive cross-coupled
injection-locked frequency dividers,”Analog Integr Circ Sig Process, 88:97–104,
2016.
[35] Y. Chao, and H. C. Luong, “Analysis and design of wide-band millimeter-wave
transformer-based VCO and ILFDs,” IEEE Trans. Circuits Syst. I, Reg. Papers,
vol. 63, no. 9, pp. 1416-1425, Sep. 2016.
[36] S.-L. Jang, M.-H. Suchen, and C.-F. Lee ” Colpitts injection locked frequency
divider implemented with a 3D helical transformer ,” IEEE Microw. Wireless
Compon. Lett., vol. 18, no. 6, pp.410-412, June, 2008.
[37] S.-L. Jang, F.-H. Chen, and J.-F. Huang, ” A transformer-coupled LC-tank
injection locked frequency divider,” Microw. Opt. Technol. Lett. Vol. 50, no. 3,
pp.592-595, Mar. 2008.
[38] S.-L. Jang, C.-C. Liu and C.-W. Tai, ” Implementation of 6-port 3D transformer
in injection-locked frequency divider,” IEEE Int. VLSI- DAT, 2009.
[39] J. Zhang, H. Liu, Y. Wu, C. Zhao, K. Kang, " Analysis and design of ultrawideband
mm-wave injection-locked frequency dividers using transformer-based
high-order resonators,” IEEE J. Solid-State Circuits, 2018.
[40] Y.-H. Lin, and H. Wang, “Design and analysis of W-band injection-locked
frequency divider using split transformer-coupled oscillator technique,” IEEE
Trans. Microw. Theory Techn., vol. 66, no. 1, pp. 177–186, Mar. 2018.
[41] S.-L.Jang, Y.-J. Chen, C.-H. Fang and W. C. Lai, ” Enhanced locking range
technique for frequency divider using dual-resonance RLC resonator,”
Electron. Lett., vol. 51, 23, pp.1888-1889, 2015.
[42] S.-L. Jang, W.-C. Cheng and C.-W. Hsue, ” Triple-resonance RLC-tank divideby-
2 injection-Locked frequency divider,” Electron. Lett., Vol. 52 No. 8 pp. 624–
626, 2016.
[43] S.-L. Jang, W.-C. Cheng and C.-W. Hsue, "Wide-locking range divide-by-3
Iniection-locked frequency divider using 6th-order RLC resonator," IEEE Trans.
VLSI Syst., vol. 24, no. 7, pp.2598-2602, 2016.
[44] S.-L. Jang, and C.-Y. Lin, ” A wide-locking range Class-C injection-locked
frequency divider,” Electron. Lett., vol. 50, 23, pp.1710-1712, 2014.
[45] S.-L. Jang, F.-B. Lin, and J.-F. Huang,” Wide-band divide-by-2 injection-locked
frequency divider using MOSFET mixers DC-biased in subthreshold region,” Int.
J. Circ Theor App, 43, 2081-2088, 2015.
[46] S.-L. Jang, L.-Y. Huang, C.-W. Hsue, and J.-F. Huang," Injection-locked
frequency divider using injection mixer DC-biased in sub-threshold," IEEE
Microw. Wireless Compon. Lett., vol. 25, no. 3, pp. 193-195, March 2015.
[47] Y.-H. Chuang, S.-H. Lee, R.-H. Yen, S.-L. Jang, J.-F. Lee and M.-H. Juang, “A
wide locking range and low voltage CMOS direct injection-locked frequency
divider,” IEEE Microw. Wireless Compon. Lett., vol. 16, no. 5, pp. 299-301, May
2006
[48] S.-L. Jang, S.-S. Huang, J.-F. Lee and M.-H. Juang,” LC-tank Colpitts injectionlocked
frequency divider with record locking range,” IEEE Microw. Wireless
Compon. Lett., pp.560-562, Aug. 2008.
[49] S.-L. Jang, Z.-H. Wu, C.-W. Hsue and H.-F. Teng,” Wide-locking range dual-band
injection-locked frequency divider,” Microw. Opt. Technol. Lett. vol.55, 10, pp.
2333–2337, Oct. 2013.2009.
[50] S.-L.Jang, ” Divide-by-3 injection-locked frequency dividers using dualresonance
resonator,”Analog Integr Circ Sig Process., vol. 85, no.2, pp 335-341,
Nov.,2015.
[51] S.-L.Jang, S.-J. Jian, and C.-W. Hsue, ” Frequency tuning hysteresis of a Dualresonance
÷3 cross-coupled injection-locked frequency divider,”IET Microw.
Antennas Propag., 2018
[52] S.-L. Jang, S.-J. Jian and C.-W. Hsue," Wide-band divide-by-4 injection-locked
frequency divider using harmonic mixer," IEEE Microw. Wireless Compon. Lett.,
924-926, Oct. 2017.
[53] S. Kang, B. Choi, and B. Kim, “Linearity analysis of CMOS for RF application,”
IEEE Trans. Microw. Theory Techn., vol. 51, no. 3, pp. 972–977, Mar. 2003.
[54] J. Lee, S. Lee, H. Bae, S. Kim, “A concurrent dual-band VCO with dual resonance
in single resonator, “ Silicon Monolithic Integrated Circuits in RF Systems, pp.
135-138, 10-12 Jan. 2007.
[55] S.-L. Jang, C.-M. Chang and M.-H. Juang, ” Divide-by-2 injection-locked
frequency divider implemented with two shunt 4th-order LC resonators,” Analog
Integr Circ Sig Process, published online, 2017.
[56] H. Wu and A. Hajimiri, “A 19 GHz 0.5 mW 0.35 um CMOS frequency divider
with shunt-peaking locking-range enhancement,” in IEEE ISSCC Dig. Tech., Feb.
2001, pp. 412–413.
[57] X. Yu, A. El-Gouhary, and N. M. Neihart, “A transformer-based dual-coupled
triple-mode CMOS LC-VCO,” IEEE Trans.Microw.Theory Techn., vol. 62, no. 9,
pp. 2059–2070, 2014.
[58] A. Li, and H.-C. Luong, “A reconfigurable 4.7–6.6GHz and 8.5–10.7GHz
concurrent and dual-band oscillator in 65nm CMOS, ” Proc. IEEE Radio
Frequency Integrated Circuits Symp.,2012, vol., no., pp.523,526, 17-19 June 2012.
[59] Z. Safarian and H. Hashemi, “Wideband multi-mode CMOS VCO design using
coupled inductors,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 8, pp.
1830–1843, Aug. 2009.
[60] Amarjit Kumar, “A compact reconfigurable concurrent dual-band Wilkinson
power divider for noninvasive vital sign detection applications,” Signal
Propagation and Computer Technology (ICSPCT), 2014 International
Conference on,12-13 July 2014.