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研究生： Antony Hutahaean
Antony - Hutahaean
論文名稱： 14位元500MS/s高精度電流導向式數位至類比資料轉換器
A 14-bit 500MS/s High Accuracy Current-Steering CMOS DAC
指導教授： 陳伯奇
Poki Chen
口試委員: 鍾勇輝
Yung-Hui Chung
方劭云
Shao-Yun Fang
陳信樹
Hsin-Shu Chen
黃育賢
Yuh-Shyan Hwang
學位類別： 碩士
Master
系所名稱： 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年： 2015
畢業學年度： 103
語文別： 英文
論文頁數： 71
中文關鍵詞： 數位至類比轉換器 、誤配 、佈局樣式 、蒙地卡羅模擬 、高精度 、抗突波器。
外文關鍵詞： Digital-to-analog converter (DAC), deglitcher.
相關次數： 點閱：270  下載：29 
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  •  上一筆

    • 本論文將透過聯電 0.18um 混合模式射頻 1P6M CMOS 製程設計一顆 14 位元、500 MS/s 的高精度電流導向式數位至類比轉換器。為了達足夠的精確度，本論文將提出適合多重元件之高匹配佈局法。透過此泛用型法則，工程師可隨意挑選適合自己發想與精確程度的佈局方式以實現相關創意。
    此數位至類比轉換器將以分段式架構實現所提出之佈局樣式。最高的八個位元透過溫度計解碼器由二進位轉成溫度計碼，用來控制單位電流源矩陣的輸出，而所提出之高精度佈局樣式的主要功能在於消除電流源矩陣的系統誤配。為實現高輸出阻抗，我們採用3.3V的MOS電晶體來建構疊接電流源，其尺寸由蒙地卡羅模擬決定，而最終的電流源矩陣佈局則是透過操控軟體以自動化的方式實現。較低的六個位元則是以二進位的分流電路構建以提升精度。切換器搭配抗突波電路以抑制電流切換時所需面對的突波效應。由模擬的結果可知，整體與差動非線性誤差分別是 0.1 與 0.09 LSB，而 240 MHz 下的無雜波動態範圍達 80.8 dB，總面積為 1.32*1.52mm2，成效良好。

    A 14-bit 500MS/s high accuracy current-steering digital-to-analog converter (DAC) was designed in UMC 0.18um Mixed-Mode RF CMOS 1P6M process. To achieve a high accuracy, a general methodology to construct highly matched layout pattern for multiple-device was proposed in this thesis. With this general methodology, the engineers will be free to choose a layout pattern according to their innovation and the level of circuit precision.
    DAC was implemented in segmented architecture to implement the proposed layout pattern. The eight most significant bits are decoded from binary to thermometer code in the thermometer decoder, which steers the unary weighted current source array. The systematic mismatch of this current source array is canceled by highly matched layout pattern. To achieve higher output impedance, a 3.3 Volt CMOS model was used in cascade current source. The size of current sources was decided through Monte Carlo simulation, and the layout of current source array made by layout automation. The six bit least significant bits are implemented by binary weighted current divider circuit to enhance accuracy and update rate. And proposed switch and deglitcher were implemented to reduce the current glitch. The simulation on integral and differential nonlinearity performance are 0.1 and 0.09 LSB, respectively; the spurious-free dynamic range is 80.8 dB at 240 MHz and total area allocation is 1.32*1.52mm2.

    Acknowledgements iii 中文摘要 iv Abstract v Table of Contents vii List of Figures xi List of Tables xiv Chapter 1 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 3 Chapter 2 4 Mismatch and Layout Pattern 4 2.1 Process Variation 4 2.2 Mismatch in Integrated Circuits 5 2.2.1 Random Mismatch 7 2.2.2 Systematic Mismatch 9 2.2.3 Pelgrom's Model 11 2.3 Multi-Device Layout Matching 13 Chapter 3 20 Digital to Analog Data Converter Layout 20 3.1 Proposed Binary Weighted DAC Layout 20 3.2 Proposed Thermometer Code DAC Layout 23 3.2.1 Generate random matrix unit 23 3.2.2 Comparison of different methods of flipping 27 Chapter 4 31 Implementation of Current Steering DAC 31 4.1 Introduction 31 4.2 The Architecture of the Proposed DAC 33 4.3 The MSB Current Cell 34 4.3.1 INL Yield and Standard Deviation of Current Cell 35 4.3.2 Process parameter and Gate Overdrive (VOV) 37 4.3.3 Output Impedance 38 4.3.4 The Current Cell 40 4.3.5 The Current Buffer 43 4.4 The LSB Current Cell 44 4.5 The Digital Circuit 46 4.5.1 Column and Row Decoder 47 4.5.2 Small Decoder 48 4.5.3 Level Shifter 49 4.6 The Switch and Deglitch Latch 50 4.7 Signal Synchronization 53 Chapter 5 55 Layout Implementation and Simulation Results 55 5.1 Layout Implementation 55 5.1.1 MSB layout automation 55 5.1.2 LSB current source layout 56 5.1.3 Switches and deglitcher layout 59 5.1.4 Layout Plan 61 5.2 Static Simulation 62 5.2.1 INL 62 5.2.2 DNL 64 5.3 Dynamic Simulation 66 5.4 Performance Summary 67 Chapter 6 69 Conclusion 69 References 70

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