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研究生: 許家偉
Chia-wei Hsu
論文名稱: 穿隧型場效多晶矽薄膜電晶體之通道工程
Channel Engineering of Tunneling-Field-Effect Poly-Si Thin-Film Transistors
指導教授: 莊敏宏
Miin-Horng Juang
口試委員: 張勝良
Sheng-Lyang Jang
徐世祥
Shih-Hsiang Hsu
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2013
畢業學年度: 101
語文別: 英文
論文頁數: 91
中文關鍵詞: 穿隧型場效多晶矽薄膜電晶體
外文關鍵詞: Tunneling-Field-Effect Poly-Si Thin-Film Transis
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隨者電子產業的進步,傳統型金氧半電晶體在微型化之後面臨一些可靠度問題,例如短通道效應、熱載子效應、汲極引起位障降低效應、閘極引起汲極漏電流效應。然而,在高度微型化的過程中,穿隧型場效電晶體可以提供較小的短通道效應、小的熱載子效應以及降低汲極引起位障降低。較可以解決因微型化而造成的可靠度問題。
儘管穿隧型場效電晶體能改善傳統金氧半電晶體的缺點,但是還是面臨一些需要被解決的問題。此論文目的就是透過元件結構的改變以及相關參數模擬分析來實踐獲得高性能的穿透式場效電晶體。由於碳化矽有比矽更大的能隙,所以碳化矽和矽的結合可以在源極產生較大的電場,使得碳化矽通道的堆疊結構可以比矽通道獲得更大的導通電流。
另外一方面,因為矽化鍺有比矽更小的能隙,所以我們可以藉由矽化鍺通道的堆疊結構來造成比矽通道還大的導通電流。同時,也可以造成比鍺通道有更效的關閉電流。


In the progress of the electronics industry, the scale down of conventional metal oxide semiconductor thin film transistor (MOSFET) will emerge some reliability problems, such as short-channel effect, hot- carrier effect, drain-induce barrier lowering (DIBL) and gate-induced drain leakage (GIDL). However, the scale down of tunneling-field-effect transistor would not encounter the above issues.
Although tunneling-field effect transistor (TFET) can improve disadvantages of conventional MOSTFT, some problems of TFET are still needed to be resolved. To obtain higher-performance TFET in this study, the design of new device structure and the analysis of device relative parameters are carried out via process and device simulation. The poly-SiC has a larger energy band gap than the poly-Si. Hence, the stacked poly-Si/poly-SiC channel layer can lead to a larger on-state current than the single poly-Si channel layer, due to higher electric field at source region.
On the other hand, the poly-SiGe has a smaller energy band gap than the poly-Si. Hence, the stacked poly-Si/poly-SiGe channel layer can show a larger current than the single poly-Si channel layer, whereas the stacked poly-Si/poly-SiGe channel layer would show a smaller off-state current than the single poly-SiGe channel layer.

Abstract (Chinese)..................................................I Abstract.................................................III Acknowledgement (Chinese)..................................................V Contents..................................................VI Table Lists...................................................VIII Figure Captions...........................................IX Chapter 1 Introduction...............................................1 1-1 Conventional MOSFET device.............................2 1-1-1 Short-channel effects................................2 1-1-2 Drain-induced barrier lowering (DIBL)................3 1-2 Conventional TFET device...............................4 1-2-1 TFET device operating principle......................4 1-3 Motivation.............................................5 1-4 Thesis organization....................................6 Chapter 2 Device Scheme...................................11 2-1 The TFET structure with the single poly-Si channel layer.....................................................12 2-2 The TFET structure with the stacked poly-Si/poly-SiC channel layer.............................................20 2-3 The TFET structure with the stacked poly-Si/poly-SiGe channel layer.............................................28 Chapter 3 Results and discussion..........................36 3-1 The poly-Si p-channel TFET and the stacked poly-Si/poly-SiC p-channel TFET........................................36 3-2 The poly-Si n-channel TFET, the poly-SiGe n-channel TFET and the stacked poly-Si/poly-SiGe n-channel TFET..........52 Chapter 4 Conclusions.....................................71 Reference.................................................72

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