研究生: |
楊惠清 Hui-Ching Yang |
---|---|
論文名稱: |
MAZU-FTL: Multilevel Plane Allocation with Zippy Utilization for 3D Charge-Trap NAND Flash MAZU-FTL: Multilevel Plane Allocation with Zippy Utilization for 3D Charge-Trap NAND Flash |
指導教授: |
謝仁偉
Jen-Wei Hsieh |
口試委員: |
陳雅淑
Ya-Shu Chen 吳晉賢 Chin-Hsien Wu 張立平 Li-Pin Chang 謝仁偉 Jen-Wei Hsieh |
學位類別: |
碩士 Master |
系所名稱: |
電資學院 - 資訊工程系 Department of Computer Science and Information Engineering |
論文出版年: | 2020 |
畢業學年度: | 108 |
語文別: | 英文 |
論文頁數: | 41 |
中文關鍵詞: | 快閃記憶體 、固態硬碟 |
外文關鍵詞: | NAND flash, SSD |
相關次數: | 點閱:159 下載:0 |
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With the increasing demand for high speed storage device, the NAND flash has gained a broad market share, especially from the embedded devices and the servers. In recent years, the 3D integrated circuit technology of NAND flash has achieved great success. The cost also gradually decreases as the stacked layers and the storage density increasing. The 3D charge trap flash has become the mainstream product in today's market. It is worth noting that the 3D charge
trap flash has unique characteristics of different page access speed within the same block due to its fabrication method. Therefore, we redesign a new Flash Translation Layer (FTL) referred as MAZU-FTL for the 3D charge trap flash that contains the following three points. 1) Ability to take advantage of page access speed differences. 2) Support the NAND flash advanced commands. 3) Minimize additional memory overhead. The first two points focus on the improvement of the overall performance of the storage device, and the last point makes MAZU-FTL easy to implement. The experiment results shows that our mechanism can averagely increase write throughput by 32\% and read throughput by 65.8\%,and only requires several KB extra memory under the same 3D charge trap flash device compared to the traditional page-level FTL.
With the increasing demand for high speed storage device, the NAND flash has gained a broad market share, especially from the embedded devices and the servers. In recent years, the 3D integrated circuit technology of NAND flash has achieved great success. The cost also gradually decreases as the stacked layers and the storage density increasing. The 3D charge trap flash has become the mainstream product in today's market. It is worth noting that the 3D charge
trap flash has unique characteristics of different page access speed within the same block due to its fabrication method. Therefore, we redesign a new Flash Translation Layer (FTL) referred as MAZU-FTL for the 3D charge trap flash that contains the following three points. 1) Ability to take advantage of page access speed differences. 2) Support the NAND flash advanced commands. 3) Minimize additional memory overhead. The first two points focus on the improvement of the overall performance of the storage device, and the last point makes MAZU-FTL easy to implement. The experiment results shows that our mechanism can averagely increase write throughput by 32\% and read throughput by 65.8\%,and only requires several KB extra memory under the same 3D charge trap flash device compared to the traditional page-level FTL.
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