本論文之頻率合成器使用UMC 0.18μm製程，以Full-custom設計流程來實現，並以ISM-band 5.725GHz~5.875GHz為標的，設計工作頻段5.04GHz~5.175GHz的頻率合成器，我們除了將Delta-Sigma調變器(Δ-Σ Modulator)加以設計外，也將以往的充電汞(Charge Pump)電路及迴路濾波器使用計數器及數位濾波器來取代，數位控制振盪器(DCO)採用一般常見的LC-tank架構，在架構中使用了10組可變電容(varactor)與一組4對1多工器，來控制11-bit dco_code，可提供2048個不同的輸出頻率，數位控制振盪器的振盪頻率約為4.802GHz~5.455GHz，而其解析度在各個Corner之下介於0.0109 ps ~ 0.0127 ps。系統功率消耗約為29.47mW、晶片面積約為2.607〖mm〗^2。

This thesis presents a 5.04GHz~5.175GHz 4^th order PLL frequency synthesizer in UMC 0.18μm CMOS process. A hardware-simplified MASH 111Δ-Σ modulator is used in the frequency synthesizer. The conventional charge pump and the loop filter structure are replaced by a counter and a digital filter. An LC-tank digital-controlled oscillator (DCO) was designed. Ten pairs of symmetrical PMOS varactors are connected in parallel in the tank circuit. The DCO’s output frequency range is from 4.802GHz to 5.455GHz and its period resolution is between 0.0109ps and 0.0127ps in different corners. The power consumption is 29.47mW, and the chip size is around 2.607〖mm〗^2.

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