現代通訊的普及，在傳遞資料上可能受到第三方的攻擊，導致資料的不完整。為了解決資料完整性的問題，人們便開始制定一系列的相關標準，其中以安全雜湊演算法(SHA-3)最為普遍。SHA-3演算法除了可以驗證收到的資料是否為完整外，也可以搭配其它的加密演算法完成資料的認證、安全與完整性。
SHA-3家族分成了兩類，一類是加密雜湊函數而另一類則是可擴展輸出函數。本論文則是採用SHA-3加密雜湊函數，因為它擁有更高的安全性的模式可以做選擇，共有四種模式，分別為SHA3-224、SHA3-256、SHA3-384以及SHA3-512。為了增加使用上的彈性，完成的SHA-3 IP模組也採用在微控制器系統中最具普遍性的AXI-4界面，以方便與其它系統界接與使用。
完成的SHA-3 IP已經使用Xilinx ISE 的Virtex 5、Virtex 6、Virtex 7，以及TSMC 0.18-μm的ASIC模擬與驗證。其結果如下：使用Virtex 5 時，最高操作頻率為208.3 MHz，吞吐量為10.00 Gpbs，使用1,317個slices；使用Virtex 6時，最高操作頻率為222.22 MHz，吞吐量為10.67 Gpbs，使用1,125個slices；使用Virtex 7時，最高操作頻率為285.71 MHz，吞吐量為13.71 Gpbs，使用1,010個slices。在元件庫設計的部分，最大工作頻率為83.33 MHz，吞吐量為 4.00 Gpbs，整體晶片面積為1,700.01 μm × 2,027.55 μm，晶片核心面積為1,400.10 μm × 1,657.22 μm，消耗的功率為34.0781 mW。
關鍵字：SHA-3、第三代安全雜湊演算法、雜湊函數加密標準、AXI匯流排。

With the popularization of modern communication, the transmission of data may be attacked by a third party, leading to failing in data integrity. To keep the data integrity of a message, a lot of related standards are proposed. Among these, the secure hashing algorithm (SHA-3) is the most popular. The SHA-3 algorithm not only can verify the integrity of received data but can also be applied with an encryption/description algorithm to achieve the authentication, confidentiality, and integrity of a message.
The SHA-3 family can be divided into two categories, one is the cryptographic hash function and the other is the extendable-output function. The SHA-3 cryptographic hash function is used in this thesis because it has four modes that can be chosen according to the user’s requirement to arrive at the higher security. These modes are SHA3-224, SHA3-256, SHA3-384, and SHA3-512. To increase the flexibility of use, the designed SHA-3 IP is also wrapped with the AXI-4 interface, which is the most popular interface used with modern most microcomputer systems, to make easy to interface with the other systems.
The resulting SHA-3 IP has been verified with Xilinx ISE's Virtex-5, Virtex-6, and Virtex-7 families, as well as an TSMC 0.18-μm ASIC. The results are as follows. With the Virtex-5 family, the maximum operating frequency is 208.3 MHz, the throughput is 10.00 Gpbs, and the area used is 1,317 slices. With the Virtex-6 family, the maximum operating frequency 222.22 MHz, the throughput is 10.67 Gpbs, and the area used is 1,125 slices. With the Virtex-7 family, the maximum operating frequency 285.71 MHz, the throughput is 13.71 Gpbs, and the area used is 1,010 slices. With the TSMC 0.18-μm cell library, the maximum operating frequency is 83.33 MHz and the throughput is 4.00 Gpbs. The overall chip area is 1,700.01 μm × 2,027.55 μm, and the core area of the chip is 1,400.10 μm × 1,657.22 μm. The power consumption is 34.0781 mW.

Keywords：SHA-3, the third-generation security hash algorithm, hash function encryption standard, and AXI bus

[1] F. Assad, F. Elotmani, M. Fettach, and A. Tragha, "An optimal hardware implementation of the KECCAK hash function on virtex-5 FPGA," in Proceedings of the IEEE 2019 International Conference on Systems of Collaboration Big Data, Internet of Things & Security (SysCoBIoTS), pp. 1-5, Casablanca, Morocco, December 2019.
[2] G. S. Athanasiou, G. Makkas, and G. Theodoridis, "High throughput pipelined FPGA implementation of the new SHA-3 cryptographic hash algorithm," in Proceedings of the IEEE 2014 6th International Symposium on Communications, Control and Signal Processing (ISCCSP), pp. 538-541, Athens, Greece, May 2014.
[3] M. A. Elmohr, M. A. Saleh, A. S. Eissa, K. E. Ahmed, and M. M. Farag, "Hardware implementation of a SHA-3 application-specific instruction set processor," in Proceedings of the IEEE 2016 28th International Conference on Microelectronics (ICM), pp. 109-112, Giza, Egypt, December 2016.
[4] FIPS PUB 202, FEDERAL INFORMATION PROCESSING STANDARDS PUBLICATION, SHA-3 Standard: Permutation-Based Hash and Extendable-Output Functions (SHA-3), Information Technology Laboratory National Institute of Standards and Technology Gaithersburg, August 2015.
[5] T. Honda, H. Guntur, and A. Satoh, "FPGA implementation of new standard hash function Keccak," in Proceedings of the IEEE 2014 3rd Global Conference on Consumer Electronics (GCCE), pp. 275-279, Tokyo, Japan, October 2014.
[6] L. Ioannou, H. E. Michail, and A. G. Voyiatzis, "High performance pipelined FPGA implementation of the SHA-3 hash algorithm," in Proceedings of the IEEE 2015 4th Mediterranean Conference on Embedded Computing (MECO), pp. 68-71, Budva, Montenegro, June 2015.
[7] B. Jungk, “Evaluation Of Compact FPGA Implementations For All SHA-3 Finalists.” in Proceedings of 2012 The Third SHA-3 Candidate Conference, Washington, pp.1-35, DC USA, March 2012.

[8] B. Jungk and J. Apfelbeck, "Area-Efficient FPGA Implementations of the SHA-3 Finalists," in Proceedings of the IEEE 2011 International Conference on Reconfigurable Computing and FPGAs, pp. 235-241, Cancun, Mexico, November 2011.
[9] B. Jungk and M. Stöttinger, "Among slow dwarfs and fast giants: A systematic design space exploration of KECCAK," in Proceedings of the IEEE 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), pp. 1-8, Darmstadt, July 2013.
[10] M. Knezevic et al., "Fair and Consistent Hardware Evaluation of Fourteen Round Two SHA-3 Candidates," in Proceedings of in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 827-840, May 2012, Volume 20, no. 5.
[11] K. Kobayashi et al., "Prototyping platform for performance evaluation of SHA-3 candidates," in Proceedings of the IEEE 2010 International Symposium on Hardware-Oriented Security and Trust (HOST), pp. 60-63, Anaheim, CA, USA, June 2010.
[12] M. Rao, T. Newe, and I. Grout, "Efficient High Speed Implementation of Secure Hash Algorithm-3 on Virtex-5 FPGA," in Proceedings of the IEEE 2014 17th Euromicro Conference on Digital System Design, pp. 643-646, Verona, Italy, August 2014.
[13] W. Stallings, Cryptography and Network Security, Pearson, 2017.
[14] M. Sundal and R. Chaves, "Efficient FPGA Implementation of the SHA-3 Hash Function," in Proceedings of the IEEE 2017 Computer Society Annual Symposium on VLSI (ISVLSI), Bochum, Germany, pp. 86-91, Bochum, Germany, July 2017.
[15] J. Winderickx, J. Daemen, and N. Mentens, "Exploring the use of shift register lookup tables for Keccak implementations on Xilinx FPGAs," in Proceedings of the IEEE 2016 26th International Conference on Field Programmable Logic and Applications (FPL), Lausanne, pp. 1-4, Switzerland, August 2016.
[16] D. Wong, "Byte Ordering and Bit Numbering in Keccak and SHA-3", 2017, https://cryptologie.net/article/387/byte-ordering-and-bit-numbering-in-keccak-and-sha-3/.
[17] M. M. Wong, J. Haj-Yahya, S. Sau, and A. Chattopadhyay, "A New High Throughput and Area Efficient SHA-3 Implementation," in Proceedings of the IEEE 2018 International Symposium on Circuits and Systems (ISCAS), pp. 1-5, Florence, Italy, May 2018.
[18] 張祐崧，基於AXI-4界面的管線式AES矽智財設計與驗證，碩士論文-國立臺灣科技大學電子工程學系，7月 2019年。