在射頻積體電路(RFIC)中，頻率合成器扮演著重要的角色，其內部包含了相位偵測器(PFD)、充電幫浦(CP)、迴路濾波器(LF)、壓控振盪器(VCO)、除頻器(FD)。壓控振盪器需要低相位雜訊來避免相鄰雜訊訊號經由混波轉換的干擾，壓控振盪器的輸出在經由除頻器來達到降頻的工作，因此除頻器必須具有高的操作頻寬與頻率。而此論文主要研究鎖相迴路中的注入鎖定除頻器。

首先，設計一個使用3D八字型電感之寬頻注入鎖定除二除頻器，使用台積電0.18μm CMOS製程，此除頻器使用電感並聯電路之寄生電容作為共振腔，以及使用電容交叉耦合作為負電阻產生震盪。注入主動元件之偏壓及電容交叉耦合對之主動元件閘極偏壓被使用在調整除頻器的自振頻率。將此電路與其他使用八邊形電感之除頻器相比，使用八字形電感之除頻器有較低的EM幅射等級以及較小的EM雜訊接收敏感度。使用3D八字型電感作為共振腔之注入鎖定除頻器在輸入 0dBm時，鎖頻範圍為2.6至10.4 GHz(120%)，FOM值為13.6，功耗為8.8mW。

接著，設計一個使用八字型變壓器的除二注入鎖定除頻器，使用台積電0.18 μm BiCMOS製程，此除頻器藉由相同磁場去耦合兩個子電路除頻器。高頻帶及低頻帶(子電路)使用八字型電感並聯電路之寄生電容作為共振腔，以及使用電容交叉耦合作為負電阻產生震盪。注入主動元件之偏壓及電容交叉耦合對之主動元件閘極偏壓被使用在調整除頻器的自振頻率。將此電路與其他使用八邊形電感之除頻器相比，使用絞線變壓器之除頻器有較低的EM幅射等級以及較小的EM雜訊接收敏感度。此注入鎖定除頻器在輸入0dBm時，鎖頻範圍為1.5至10.2 GHz(137.2%)。

最後，設計二個注入鎖定除六除頻器，使用台積電0.18 μm BiCMOS製程，第一個除頻器使用一個低頻除二ILFD疊接一個高頻除三ILFD達到除六的效果,此ILFD在輸入0dBm時,除六的鎖頻範圍為8.4GHz至13.8GH(48.6%),而第二顆除頻器使用 CML (current-mode logic) 除二除頻器疊接使用電容交叉耦合式之除三注入鎖定除頻器所構成；CML 則為在 flip-flop 啟用上緣 clock 輸出切換 到輸入，以致於輸出頻率為輸入的一半；且負載較為小，則有較小的 RC 延遲， 但需要提高電壓來補償下降的迴路增益，做為功耗與延遲之 tradeoff。因此使用 CML 疊接 ILFD，讓直流和交流電流可以更有效使用，此ILFD在輸入0dBm時，除六的鎖頻範圍為 8.5GHz至 10.9GHz(24.7%)

Frequency synthesizer plays an important role of Radio Frequency Integrated circuit(RFIC), its blocks include Phase Frequency Detector (PFD), Charge Pump (CP), Loop Filter (LF),Voltage Controlled Oscillator (VCO), and Frequency Divider (FD). In order to pursue the most important characteristics performance of VCO and Divider, low-power, low phase noise, wide Locking range, this thesis presents the design of HEMT oscillator and Injection-Locked Frequency Dividers (ILFDs).

First, a wide-band divide-by-2 injection-locked frequency divider (ILFD) with a 3-dimensional twisted inductor in the 0.18 μm CMOS process. The ILFD uses an inductor resonator in shunt with parasitic capacitors as the resonator, and it also uses a capacitive cross-coupled pairs to generate negative resistance for start-up oscillation. The gate bias of the capacitive cross-coupled pair is used to tune the free-running ILFD oscillation frequency. As compared to other ILFDs using octagonal inductors, the ILFDs using a twisted inductive coil have low EM radiation level and less sensitive to received EM noise. For the implemented ILFD with a 3D inductor, at the power consumption of 8.8 mW and at the input power of 0 dBm, the locking range is 7.8 GHz from 2.6GHz to 10.4GHz and the figure of merit (FOM) is 13.6.

Next, a divide-by-2 injection-locked frequency divider (ILFD) with a twisted transformer in the 0.18 μm CMOS process. The ILFD consists of two sub-ILFD coupled by the common magnetic field. The high-band and low-band sub-ILFD use an inductor resonator in shunt with parasitic capacitors as the resonator, and they also uses capacitive cross-coupled pairs to generate negative resistance for start-up oscillation. The gate biases of capacitive cross-coupled pairs and injection gates are used to tune the free-running ILFD oscillation frequency. As compared to other ILFDs using octagonal inductors, the ILFDs using a twisted inductive coil have low EM radiation level and less sensitive to received EM noise. At the input power 0 dBm the operation range is 8.7GHz from 1.5GHz to 10.2GHz (137.2%).

Finally, a wide locking range ÷6 ILFD designed in the TSMC 0.18 μm BiCMOS process. The proposed current-reused ILFD is based on a low-frequency ÷2 p-core LC ILFD stacking on a high-frequency ÷3 n-core capacitive cross-coupled LC ILFD and a CMOS divide-by-6 injection-locked frequency divider (ILFD) with a divide-by-2 current-mode logic (CML) stacked on a capacitive cross-coupled oscillator used as an LC divide-by-3 ILFD. The divide-by-6 ILFD composed of two ILFDs has a locking range 5.4GHz from 8.4GHz to 13.8GHz and the other one is 2.4 GHz from 8.5 GHz to 10.9 GHz.

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