對於單晶片系統之設計，近年來提出一個發展平台稱為晶片網路。
目前研究人員在一般平行計算之領域，大部份都是研究傳統規則性之拓
樸，例如: mesh 及 hyper-cube。 然而大部份單晶片系統是針對應用
之特殊需求而特別來製定的。
通常是由各種異質元件在非規則性之拓樸下作傳送通訊。此篇論文
針對網路晶片架構提出一個完整的合成流程，發展平台分成下列幾個主
要的步驟: 把工作分配到適當的處理元件(Task assignment)，在拓樸
中把處理元件放置在最適當的位置(Node mapping)，探索最合適之拓樸
(Topology exploration) ， 以及的路由路徑分配演算法(TRAIN
algorithm)。
本篇論文主要貢獻是提出一個能自動分配工作到適當的處理元
件，分配處理元件到拓樸到適當的位置及探索一個最佳拓樸之低功率網
路晶片系統平台，使的功率消耗能有效的減少。由實驗結果顯示所提出
來的方法找出來之拓樸比Mesh 拓樸有效平均減少29%。針對四種視訊
應用，本論文提出的方法可以針對MPEG4,VOPD,PIP,和MWD 之應用分別
減少23%,29%,13%,和20%。

Network-on-Chip (NoC) has recently been proposed as a practical development platform for Systems-on-Chip (SoC) designs. Most researchers advocate the use of traditional regular networks like mesh and hyper-cube in general-purpose parallel computing.
However, most SoC platforms are special-purpose tailored to the domain-specific
requirements of their applications. They are usually built from a large diversity of heterogeneous components which communicate in irregular style.
This thesis illustrates a complete synthesis flow for customized NoC architectures, that partitions the development work into major steps(task assignment, node mapping, topology exploration, and routing algorithm). The major contribution of this thesis is to propose a framework of low power NoC system which automatically assigns task to various types of PE, maps PEs to the node of topology and selects the nearly optimal topology to reduce the power consumption. Experimental results show that the proposed method can reduce the power consumption by 29 % on average compared to mesh. For four video applications, our proposed method can reduce the power consumption 23%, 29%, 13%, and 20% on MPEG4, VOPD, PIP, and MWD, respectively.

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