在RF射頻收發機中，頻率合成器扮演著重要的角色，其內部包含了相位偵測器(PFD)、充電幫浦(CP)、迴路濾波器(LF)、壓控振盪器( VCO)、除頻器(FD)、。因為要追求低功耗、低相位雜訊與寬鎖定範圍的除頻器和震盪器特性，所以本篇論文呈現出四相位的震盪器(QVCO)和注入鎖定除頻器(ILFD)的設計，並提供一種最佳化方式萃取電感模型參數，以輔助設計電路時之所需電感。

第一部分提出了一個新的正交壓控振盪器(QVCO)，使用兩個差動的壓控振盪器 VCO 並帶有兩個 8 字形電感器，其中包括兩匝次級電感器。 差動器sub-VCO 確實使用了三級互感電感。 次級電感處於交叉耦合連接中以強制正交從兩個子 VCO 產生。在 TSMC 0.18 μm CMOS 工藝中QVCO的面積為 1,197 × 1,183 mm2。 並產生0.6 V 的電源和 2.4 mW 的功耗，在3.23 GH時的偏移頻率量測到1 MHz 的相位雜訊 為 −118.76 dBc / Hz，QVCO的figure of merit(FOM)為−185.14 dBc / Hz。
設計的第二部分提供一種電感參數萃取模型方法。精確的螺旋電感電路模型和參數提取在單晶片微波集成電路（MMIC）設計中非常重要。 本文提出了一種直接由S參數系統化建模在有損基底上的8字形電感器，並以最佳化方式來達成。

最後的部分是採用了三個真實電路分別為兩個耦合注入鎖定壓控震盪器與一個八字電感除頻器，三個電路都是採用8字電感去做設計，利用設計出來的等效模型去萃取相對應的數值，並且套用回原基本電路，進而比較其差異。

In the RF transceiver, frequency synthesizer plays an important role, its blocks include Phase Frequency Detector (PFD), Charge Pump (CP), Loop Filter (LF), Voltage Controlled Oscillator (VCO), Frequency Divider (FD), Frequency Multiplier (FM) and frequency synthesizer can be used as a Frequency Shift Keying demodulate (FSK). To pursue low-power, low phase noise, and wide locking range include of Divider and VCO, so this thesis presents the design of a quadrature voltage-controlled oscillator (QVCO) and an injection-locked frequency divider (ILFD) and provides an optimized way to extract the inductor model parameters to assist in the design of the required inductance of the circuit.

The first part is a new quadrature voltage-controlled oscillator (QVCO) with two differential VCOs with an 8-shaped inductor with two lobes, inside which a two-turn secondary inductor is included. The differential sub-VCO uses a trifilar inductor. The secondary inductors are in cross-coupled connection to enforce the quadrature generation from the two sub-VCOs. The die area of the QVCO in the TSMC 0.18 μm CMOS process is 1.197 ×1.183 mm2. At the supply of 0.6 V and the power consumption of 2.4 mW, at 1MHz offset frequency, the measured phase noise of the VCO at 3.23 GHz is −118.76 dBc/Hz, and the QVCO figure of merit is−185.14 dBc/Hz.

The second part of the design is the accurate circuit model of inductor and parameter extraction for spiral inductors is very important in monolithic microwave integrated circuit (MMIC) design. This chapter presents a systematic methodology for modeling on-chip 8-shaped inductors over a lossy substrate directly from S-parameter simulations. The model implementation neither requires precise knowledge of geometry or the fabrication process.

The last part is the use of 8-shaped inductor models for two coupled injection-locked voltage-controlled oscillators and an eight-shaped inductor frequency divider. The three circuits are designed with eight-shaped inductors, and the equivalent model is designed to Extract the corresponding value and apply it back to the original basic circuit to compare the differences.

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