近年來，無線通訊的快速發展，各種新穎晶片不斷產出，然而統整各系統子電路時，常會碰到操作時脈的不同，導致資料出現偏差，鎖相迴路在此扮演著重要的角色，典型的鎖相迴路由相位偵測器或相位頻率偵測器、充電汞、迴路濾波器、壓控振盪器和除頻器所構成。其中，壓控振盪器與除頻器的特性影響之重，使其成為核心電路，鎖相迴路藉由調整壓控振盪器產生穩定波形，來完成鎖定功能，故此，本論著重於設計高性能的壓控振盪器與注入鎖定除頻器。

在章節四中，講述了使用BiCMOS的製程設計的異質接面雙極性電晶體(HBT)壓控振盪器，並分析了所使用來抑制相位雜訊的技術，主要是靠著減少與LC共振腔並聯的HBT基-射極的寄生電容與使用疊接架構的電路，而不用去減少跨導體的元件尺寸，寄生電容的減少會造成AM-PM轉換時，閃爍雜訊因為上變頻，而對相位雜訊的貢獻成分減少，另外，疊接架構能增大電路增益，降低雜訊因子，以此得到更低的相位雜訊，並在0.18 μm BiCMOS的模擬環境中描述模擬結果，且與實際量測的相互驗證。
在章節五中，描述一個採用TSMC 0.18μm CMOS製程的LC共振腔的N/PMOSFET疊接的交錯耦合VCO，可稱為Push-Pull VCO，晶片面積為0.798 × 0.762 mm2，該VCO採用一種新設計的8字形變壓器用於提高PMOSFET的電壓振幅來實現低功耗。變壓器使用了2個各3匝線圈的電感串聯為主要電感，佈局時減少了交叉金屬線，用來減少寄生電容。單圈的8字形的次要電感與主要電感有著相當高的耦合係數，3比1圈的變壓器架構能夠更對稱的佈局，將8字形由中間劃分，會形成兩個波辦形狀，會輻射遠端磁場用來抑制磁場幅射。量測結果為在2.99 GHz時，相位雜訊為-124.9 dBc/Hz，FOM為-198.05 dBc/Hz。

在章節六中，描述了一個使用TSMC 0.18 μm CMOS製程的注入鎖定除頻器(ILFD)，該除頻器為除2且使用4個相互耦合的電感作為諧振器，且該除頻器可藉由切換VT的偏壓，會產生高頻、中頻、低頻的振盪頻率，藉此去創造寬的鎖定範圍，晶片面積為1.2×0.954 mm2，在VDD = 0.9 V時，功耗為8.8983 mW，最後，在注入0 dBm的外部訊號時，除二鎖定範圍為4.69 GHz，由2.79 GHz到7.48 GHz，鎖定範圍的百分比為91.3%。

In recent years, with the rapid development of wireless communication, a variety of novel chips have been continuously produced. However, the integration of various system sub-circuits often encounter different operating clocks, resulting in data deviations. Phase-locked loops play an important role here. Typical the phase-locked loop is composed of phase detector or phase frequency detector, charge pump, loop filter, voltage-controlled oscillator and frequency divider. Among them, the characteristics of the voltage-controlled oscillator and the frequency divider are so important that they become the core circuit. The phase-locked loop adjusts the voltage-controlled oscillator to generate a stable waveform to complete the lock function. Therefore, this thesis focuses on the design of high-performance voltage-controlled oscillator and injection locked frequency divider.

In Chapter 4, the Heterojunction Bipolar Transistor (HBT) voltage-controlled oscillator designed using the BiCMOS process is described, and the technology used to suppress phase noise is analyzed. Mainly by reducing the parasitic capacitance of the HBT base-emitter in parallel with the LC resonant cavity and the circuit using the stack structure, without reducing the component size of the transconductor. The reduction of parasitic capacitance will cause the flicker noise to reduce the contribution of phase noise due to the up-conversion during AM-PM conversion. In addition, the cascode structure can increase the circuit gain, reduce the noise factor, and obtain a lower phase noise. The simulation results are described in the simulation environment of 0.18 μm BiCMOS, and they are mutually verified with actual measurements.

In Chapter 5, a cross-coupled VCO with stacked N/PMOSFETs of LC resonator using TSMC 0.18μm CMOS process is presented, which can be called Push-Pull VCO, with a wafer area of 0.798 × 0.762 mm2. The VCO uses a newly designed 8-shaped transformer to increase the voltage swing of the PMOSFET to achieve low power consumption. The transformer uses two inductances of each 3-turn coil in series as the primary inductance, and the cross metal lines are reduced during the layout to reduce parasitic capacitance. The single-turn 8-shaped secondary inductor has a very high coupling coefficient with the first-stage inductor, and the 3:1-turn transformer architecture can be more symmetrical. The lobes at both ends of the 8-shaped radiate the far-end magnetic field to suppress the radiation of the magnetic field. The measurement result is that at 2.99 GHz, the phase noise is -124.9 dBc/Hz, and the FOM is -198.05 dBc/Hz.

In Chapter 6, an injection-locked frequency divider (ILFD) using TSMC 0.18 μm CMOS process is described. The frequency divider is divided-by-2 and uses 4 mutually coupled inductors as resonators. And the frequency divider can generate high frequency band, middle frequency band, and low frequency band oscillation frequencies by switching the bias voltage of VT to create a wide locking range. The chip area is 1.2×0.954 mm2, and when VDD = 0.9 V, the power consumption is 8.8983 mW. Finally, when an external signal of 0 dBm is injected, the locking range is 4.69 GHz, from 2.79 GHz to 7.48 GHz., the locking range percentage is 91.3%.

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