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研究生: 林聖鈞
Sheng-Chun Lin
論文名稱: 以P型通道金氧半場效電晶體控制之高驅動能力奈米尺寸電晶體
P-Channel MOSFET-Controlled Nanometer-Scale Transistor with High Driving Capability
指導教授: 莊敏宏
Miin-Horng Juang
口試委員: 徐世祥
Shih-Hsiang Hsu
張勝良
Sheng-Lyang Jang
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2020
畢業學年度: 108
語文別: 英文
論文頁數: 53
中文關鍵詞: 以P型通道金氧半場效電晶體控制高驅動能力奈米尺寸電晶體
外文關鍵詞: P-Channel MOSFET-Controlled, Nanometer-Scale Transistor with High Driving Capability
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電子科技發展迄今數十多年,已讓整個高科技產業的產品都脫離不開電子元件的使用,隨著電晶體的微縮下因而產生所謂的短通道效應,除此之外,導通電流也大幅度降低。
無接面型金氧半場效電晶體由於沒有接面的產生使其和傳統金氧半場效電晶體相比之下導通阻抗較小、輸出電流較大,然而因為缺乏相反摻雜區域,於是無法有效阻擋會引發嚴重漏電問題的擊穿現象,在此本論文提出溝渠式閘極無接面P型金氧半場效電晶體的結構來抑制漏電流情形。為了要增加輸出電流,考慮在陰極處多摻雜一塊高濃度N型區域而形成由P型金氧半場效電晶體控制之奈米尺寸雙極性電晶體的結構,導通狀態下,P-N接面會形成順向偏壓並且讓電子從陰極注入至通道,因此在閘極偏壓-2伏特、陰極偏壓-2伏特下雙極性電晶體的輸出電流大約為溝渠式閘極無接面P型金氧半場效電晶體的十二倍。
此外,藉由在陰極端的高濃度N型區域改用異質結構可以更有效地提高導通狀態下的電流,使用一寬能隙之摻雜碳的矽材料來構成陡峭接面,讓接面處價電帶的能障阻擋電洞從P型區流至N型區,而聚積的電洞能夠促進P-N接面導通,因此在閘極偏壓為-1伏特、陰極偏壓為-2伏特下原本的雙極性電晶體的輸出電流為345 μA/μm,而具有寬能隙陰極之雙極性電晶體下的輸出電流達到3138 μA/μm。


Since the development of electronic technology for decades, the products of the entire high-tech industry have been inseparable from the use of electronic components. As the transistor device scales down, so-called short channel effect may happen. In addition, the conduction current is greatly decreased ascribed to the reduced device size.
Without forming the junction, junctionless MOSFET shows smaller conduction resistance and larger output current than conventional MOSFET, but it is short of the counter-doping region which suppresses the punch-through leakage. In this thesis, a trench-gate junctionless PMOSFET structure is used to reduce the off-state leakage. To increase on-state driving current, an embedded n+ region is formed at the cathode, which shows a nanometer-scale bipolar transistor triggered by PMOSFET structure. When this bipolar device is turned on, P-N junction will be forward-biased and then considerably cause injection of electrons from cathode to the channel. As a result, the output current of bipolar device is about twelve times as much as the output current of trench-gate junctionless PMOSFET at gate bias -2 V, cathode bias -2 V.
Further, the output current can be more effectively enhanced by using the heterostructure at the n+ cathode. The wide bandgap carbon-doped Si is employed to form an abrupt P-N junction. An energy barrier appears in the valance band at the junction, which tends to retard holes to flow from p+ region to n+ region and thus the accumulated holes can facilitate the turn-on of P-N junction. Therefore, the output current of bipolar device without heterostructure is 345 μA/μm and the output current of bipolar device with wide bandgap cathode region reaches 3138 μA/μm at gate bias -1 V, cathode bias -2 V.

摘要 i Abstract ii Acknowledgment iii Contents iv Figure captions vi Table lists ix Chapter 1 Introduction 1 1-1 Motivation 1 1-1-1 Hot carrier effect 1 1-1-2 Drain-induced barrier lowering (DIBL) 2 1-2 Trench-gate junctionless PMOSFET 2 1-3 Nanometer-scale bipolar transistor triggered by PMOSFET 3 1-4 Thesis organization 4 Chapter 2 Device fabrication 5 2-1 Trench-gate junctionless PMOSFET 5 2-2 Nanometer-scale bipolar transistor triggered by PMOSFET 11 Chapter 3 Results and discussion 18 3-1 Comparison between conventional planar junctionless PMOSFET and trench-gate junctionless PMOSFET 18 3-2 Comparison between trench-gate junctionless PMOSFET and nanometer-scale bipolar transistor triggered by PMOSFET 20 3-2-1 The ID-VK curve for trench-gate junctionless PMOSFET and nanometer-scale bipolar transistor triggered by PMOSFET 20 3-2-2 The ID-VG curve for trench-gate junctionless PMOSFET and nanometer-scale bipolar transistor triggered by PMOSFET 24 3-2-3 The band diagram for trench-gate junctionless PMOSFET and nanometer-scale bipolar transistor triggered by PMOSFET 27 3-2-4 Comparison between nanometer-scale bipolar transistor triggered by PMOSFET with different n+ concentration at the cathode 28 3-3 Comparison between nanometer-scale bipolar transistor triggered by PMOSFET with and without heterostructure n+ cathode region 31 3-3-1 The ID-VK curve for nanometer-scale bipolar transistor triggered by PMOSFET with and without heterostructure n+ cathode region 32 3-3-2 The ID-VG curve for nanometer-scale bipolar transistor triggered by PMOSFET with and without heterostructure n+ cathode region 36 Chapter 4 Conclusion 39 Reference 40

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