研究生: |
張翊祥 Yi-Hsiang Chang |
---|---|
論文名稱: |
具雙路徑頻率補償技術與緩啟動功能之積體化降壓型轉換器 Dual-Path Frequency Compensation Technique and Soft-Start Mechanism for Integrated Buck Converters |
指導教授: |
羅有綱
Yu-Kang Lo 邱煌仁 Huang-Jen Chiu 劉邦榮 Pang-Jung Liu |
口試委員: |
馬紅波
none |
學位類別: |
碩士 Master |
系所名稱: |
電資學院 - 電子工程系 Department of Electronic and Computer Engineering |
論文出版年: | 2013 |
畢業學年度: | 101 |
語文別: | 中文 |
論文頁數: | 55 |
中文關鍵詞: | 補償電容 、電容放大 、直流-直流轉換器 、暫態響應 |
外文關鍵詞: | Compensation capacitor, capacitor multiplier, dc-dc converters, transient response |
相關次數: | 點閱:367 下載:5 |
分享至: |
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
本論文採用雙路徑頻率補償技術,應用於直流-直流轉換器。此技術使用兩道流向相反之電流,同時對誤差放大器輸出端的補償電容進行充放電。此方法不僅可有效縮小補償電容值,亦可改善轉換器的暫態響應。論文中也提出一緩啟動機制,利用信號控制電流流入電容時間,使參考位準以階梯式方式遞增,以實現抑制浪湧電流與過充電壓。兩種技術皆具有電容放大效應,使得補償電容與緩啟動電容易於製作於晶片內部,以減少外接元件需求。
本轉換器使用TSMC 0.35 μm 2P4M CMOS製程來實現,晶片面積為1.780×1.977 mm2,輸入電壓5 V而輸出電壓3.3 V,外接電感與電容分別為4.7 μH與10 μF,切換頻率則是1 MHz。與其他參考文獻相比,雙路徑電容放大技術能將所需的補償電容值縮小百倍,且當負載電流由50 mA變化至500 mA時,轉換器回復時間小於18 μs。緩啟動電路則有效抑制浪湧電流與過充電壓。
This thesis presents a dual-path frequency compensation technique and implements the technique in a dc-dc converter. This compensation technique uses two currents, whose directions are reversed, to simultaneously charge and discharge the compensation capacitor of the error amplifier. This method not only has capacitor multiplier effect, but also improves the transient response of the dc-dc converter. This thesis also introduces a novel soft-start circuit that uses a signal to control a charging current value into the capacitor of the soft-start circuit. As a result, the voltage reference of the error amplifier increases slowly as a stair-case signal to prevent inrush current and output voltage overshoot during the start-up period. Both of two techniques have capacitor multiplier effect, so the compensation capacitor and soft-start capacitor are easy to be integrated into on-chip. Therefore, it leads to a reduction in external components.
This converter had been fabricated with TSMC 0.35-μm 2P4M CMOS process, and its chip size is 1.173×1.146 mm2. The input voltage is 5 V and the output voltage is 3.3 V. The off-chip inductance and capacitance are 4.7 μH and 10 μF, respectively. The switching frequency is 1 MHz. To compare with other references, the value of compensation capacitor can be reduced by hundred times with dual-path frequency compensation technique and the transient recovery time of the dc-dc converter is less than 18 μs for the load current changing between 50 mA and 500 mA.
[1]S. Pennisi, “CMOS Multiplier for Grounded Capacitors,” Electronic Letters, vol. 38, no. 15, pp. 765-766, Jul. 2002.
[2]K. H. Chen, C. J. Chang, and T. H. Liu, “Bidirectional Current-Mode Capacitor Multipliers for On-Chip Compensation,” IEEE Trans. Power Electron., vol. 23, no. 1, pp.180-188, Jan. 2008.
[3]Y. Tang, M. Ismail, and S. Bibyk, “Adaptive Miller Capacitor Multiplier for Compact On-Chip PLL Filter,” Electronic Letters, vol. 39, no. 1, pp. 43-45, Jan. 2003.
[4]G. A. Rincon-Mora, “Active Capacitor Multiplier in Miller-Compensated Circuits,” IEEE J. Solid-State Circuits, vol. 35, no. 1, pp. 26-32, Jan. 2000.
[5]Y. Koo, H. Huh, Y. Cho, J. Lee, J. Park, K. Lee, D. K. Jeong, and W. Kim, “A Fully Integrated CMOS Frequency Synthesizer with Charge-Averaging Charge Pump and Dual-Path Loop Filter for PCS- and Cellular-CDMA Wireless Systems,” IEEE J. Solid-State Circuits, vol. 37, no. 5, pp. 536-542, May 2002.
[6]W. R. Liou, P. H. Chen, M. L. Yeh, and C. T. Kuo, “A Dual-Mode Step-Up DC/DC Converter IC with Current-Limiting and EMI Reduction Techniques,” International Conference on Communication Circuits and Syst., pp. 1332–1336, May 2008.
[7]C. F. Lee and P. K. T. Mok, “A Monolithic Current-Mode CMOS DC-DC Converter with On-Chip Current-Sensing Technique,” IEEE J. Solid-State Circuit, vol. 39, no. 1, pp. 3-14, Jan. 2004.
[8]W. Yan, W. Li, and R. Liu, “A Noise-Shaped Buck DC-DC Converter with Improved Light-Load Efficiency and Fast Transient Response,” IEEE Trans. Power Electronic., vol. 26, no. 12, pp. 3908–3924, Dec. 2011.
[9]Y. Y. Mai and P. K. T. Mok, “A Constant Frequency Output-Ripple-Voltage-Based Buck Converter without Using Large ESR Capacitor,” IEEE Trans. Circuits Syst. II, vol. 55, no. 8, pp. 1150-1154, Aug. 2008.
[10]K. Umimura, H. Sakurai, and Y. Sugimoto, “A CMOS Current-Mode DC-DC Converter with Input and Output Voltage-Independent Stability and Characteristics Utilizing a Quadratic Slope Compensation Scheme,” in Proc. Solid-State Circuits conference, pp. 178-181, Sep. 2007.
[11]K. H. Chen, H. W. Huang, and S. Y. Kuo, “Fast-Transient DC-DC Converter with On-Chip Compensated Error Amplifier,” IEEE Trans. Circuits and Syst. II, vol. 54, no. 12, pp. 1150-1154, Dec. 2007.
[12]F. F. Ma, W. Z. Chen, and J. C. Wu, “A Monolithic Current-Mode Buck Converter with Advanced Control and Protection Circuits,” IEEE Trans. Power Electronic., vol. 22, no. 5, Sep. 2007.
[13] C. Y. Leung and P. K. T. Mok, “An Integrated CMOS Current-Sensing Circuit for Low-Voltage Current-Mode Buck Regulator,” IEEE Trans. Circuits and Syst., vol. 52, no. 7, Jul. 2005.
[14] Y. Wu, Y. S. Tsui and P. K. T. Mok, “Area- and Power-Efficient Monolithic Buck Converters with Pseudo-Type III Compensation,” IEEE J. Solid-State Circuits, vol. 45, no. 8, pp. 1446–1455, Aug. 2010.
[15] P. E. Allen and D. R. Hoolberg, “CMOS Analog Circuit Design,” New York: Oxford. 2002.
[16] Behzad Razavi, “Design of Analog CMOS Integrated Circuit,” Boston, MA:McGraw-Hill, 2001.
[17] 梁適安,「交換式電源供應器之理論與實務設計」,二版,全華科技圖書,2008年。
[18] 徐稚堯,「採用雙路徑電容放大技術之降壓轉換器」,國立台灣科技大學電子工程系研究所碩士論文,2012。
[19] 康洛誠,「脈波省略緩啟動電路之電流模式降壓轉換器」,國立台灣科技大學電子工程系研究所碩士論文,2012。