本論文提出兩個以利用現場可程式化閘陣列(FPGA)所實現的電路架構，分別是以鎖相迴路(PLL)與延遲矩陣所設計之數位至時間轉換器(DTC) ，與基於脈衝縮放延遲線(PSDL)設計的數位脈波寬度調變(DPWM)電路。並探討FPGA在受限的設計環境下實現本論文所提出架構的利弊得失。
本論文介紹了兩種高精度DTC的設計方法，兩者以不同的技術對PLL進行精細控制，並受益於PLL負迴授的特性使得各級延遲在外部環境影響下保持較高一致性，透過延遲迴繞(Wrapping)效應所產生的延遲與相位轉換，設計出高精度低抖動DTC。兩種DTC分別以兩塊FPGA: Intel Altera Stratix IV與Xilinx Virtex-6實現。Stratix IV時間解析度為2ps、微分非線性(DNL)為-3.6 ~ 3.25 LSB、積分非線性(INL)為-2.5 ~ 3.0 LSB，輸出抖動(Jitter)則是4.9 LSB。Virtex-6解析度是1.94ps、DNL是-3.3 ~ 3.7 LSB、INL是-2.8 ~ 2.7 LSB，Jitter則是8.9 LSB。
本論文同步提出一種高精度DPWM設計。利用PLL實現工作週期分割，搭配延遲元件的脈衝縮放特性，為提升元件解析度提供了嶄新的想法。此架構於Intel Altera Stratix IV與Arria 10這兩種FPGA實現。其中Stratix IV時間解析度為4.8ps、DNL是-3.0~2.9 LSB、INL是-3.0~2.9 LSB，Jitter則是3.6 LSB，Arria 10解析度是6.1ps、DNL是-2.2~2.7 LSB、INL是-1.5~1.6 LSB，Jitter則是2.8 LSB。

This thesis proposes two new architectures implemented wit Field Programmable Gate Arrays (FPGA). One is Digital-to-Time Converter (DTC) composed of a Phase-Locked Loop (PLL) and a Delay Matrix. The other is Pulse-Shrinking Delay Line (PSDL) based Digital Pulse Width Modulation (DPWM). The pros and cons of proposed architecture due to the limited design environment and abundant design resources of FPGA will be discussed in detail.
This thesis presents two high-precision DTCs. Both use different techniques to finely control the PLL to be benifited by the negative feedback of PLL to reduce the impact of the PVT variations on the respective high accuracy delays. Based on the delay wrapping, a high-precision low-jitter DTC is realized. The DTCs are implemented with two FPGAs: Intel Altera Stratix IV and Xilinx Virtex-6. Stratix IV DTC has a time resolution of 2ps, differential nonlinearity (DNL) of -3.6 ~ 3.25 LSB, integral nonlinearity (INL) of -2.5 ~ 3.0 LSB, and output jitter (Jitter) of 4.9 LSB. Virtex-6 DTC has 1.94ps resolution, -3.3 ~ 3.7 LSB DNL, -2.8 ~ 2.7 LSB INL and 8.9 LSB Jitter.
This thesis also proposes a high-precision DPWM. PLL is used for duty cycle division which is combined with the Pulse-Shrinking delay elements to provide a brand new architecture for improving DPWM resolution. This circuit is implemented with two FPGAs, Intel Altera Stratix IV and Arria 10. The Stratix IV version has 4.8ps resolution, -3.0~2.9 LSB DNL, -3.0~2.9 LSB INL and 3.6 LSB Jitter. The Arria 10 version has 6.1ps resolution, -2.2~2.7 LSB DNL, -1.5~1.6 LSB INL and 2.8 LSB jitter.

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