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研究生： 龍純瑜
Chun-Yu Lung
論文名稱： 基於HEVC系統之低複雜度小數運動估測架構與電路實現
The VLSI Architecture of a Low Complexity Fractional Motion Estimation for HEVC Systems
指導教授： 沈中安
Chung-An Shen
口試委員: 阮聖彰
Shanq-Jang Ruan
林昌鴻
Chang Hong Lin
學位類別： 碩士
Master
系所名稱： 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年： 2015
畢業學年度： 104
語文別： 英文
論文頁數： 47
中文關鍵詞： 高效率影像編碼(HEVC) 、小數運動估測 、插值系統 、影像編碼
外文關鍵詞： fractional motion estimation
相關次數： 點閱：235  下載：4 
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    • 隨著科技的進步，視訊影像技術已越來越發達，並在現今生活中扮演不可或缺的角色。然而，隨著視訊影像的進步，影像壓縮演算法的設計也日趨複雜，進而造成面積過度的消耗與運算複雜度的上升。
    有鑑於此，本論文設計並實現一個基於超大型積體電路之低複雜度小數運動估測架構與電路。在此設計中，我們透過最佳化插值系統的處理流程以達到硬體共用，同時降低系統運算量。此外，針對絕對差值轉換和系統的架構改良，我們利用管線化時間多工的方式來達成；同時也使用了線性生成四分之一像素的方式來降低整體小數運動估測系統的複雜度。
    在本論文中，我們將詳細介紹所提出的小數運動估測硬體架構及電路實現。本設計是在台積電90奈米製程的環境下實現。Post-layout的實驗結果顯示，在消耗525.4k的邏輯閘數之下，此小數運動估測系統可以處理3840 × 2176 像素(Ultra HD resolution)達每秒38張；與其它支援HEVC小數運動估測系統的電路相比較，我們還能增進0.4-1.2 dB的影像品質。

    This thesis presents the VLSI architecture and circuit implementation of a low complexity Fractional Motion Estimation (FME) for High Efficient Video Coding (HEVC) systems. In this design, the processing sequences of input pixels are highly optimized so that large parts of the hardware resources in the interpolator circuit are shared and the area complexity is greatly reduced. Furthermore, the Sum of Absolute Transformed Differences (SATD) circuit is realized by the employment of a pipelined time-multiplexing scheme, in order to improve the efficiency of hardware utilization and to maintain high processing throughput. Moreover, the bilinear quarter pixels estimation approach is used to reduce the computation complexity of both the interpolator and SATD circuits. The proposed FME circuit has been synthesized, placed and routed through cell-based design flow using TSMC 90nm technology. The post-layout estimations show that, occupying the area complexity of 525.4 kGE, the presented FME engine can achieve 38 frames per second (fps) with image resolution of 3840 × 2176 and 28 fps with resolution of 7680×4352. In addition, comparing to the literature based on HEVC systems, this design enhances the Rate-Distortion (RD) performance with 0.4-1.2 dB by supporting more prediction modes.

    摘要 IV Abstract V 誌謝 VI Outline VII Figures IX Tables XI I. Introduction 1 1.1 Background 1 1.2 Previous works 2 1.3 Contributions 3 1.4 Organizations 4 II. Overview of the Fractional Motion Estimation 5 2.1 Video Coding Basics 5 2.2 Processing Units of HEVC systems 7 2.3 Fundamentals of Fractional Motion Estimation 8 2.3.1 Interpolation 8 2.3.2 Sum of Absolute Transformed Differences (SATD) 10 III. The Proposed FME Architecture 15 3.1 Design Challenges 15 3.2 Architectural Overview and Prediction Modes 16 3.3 The Proposed Interpolator Architecture 18 3.4 The Proposed SATD Architecture for Half Pixels 25 3.5 The Proposed SATD Architecture for Quarter pixels 34 IV. The Experimental Results 36 5.1 Rate-Distortion Cost Performance 36 5.2 Timing Analysis 37 5.3 Post-layout Experimental Results 39 5.4 Comparisons with Prior Arts 41 V. Conclusion 44 References 45

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