本論文使用UMC 90nm 1P9M CMOS製程，首先設計適用於GSM、GPS、WCDMA、IEEE 802.11b/g及UWB group-1、WiFi等通訊協定的低雜訊放大器，配合軟體定義無線電(Software Defined Radio，SDR)系統，軟體改變行動裝置使用的通訊協定。在此，低雜訊放大器設計在兩個頻段，分別為0.8 ~ 2.4 GHz(低頻段)與3 ~ 6 GHz(高頻段)，包含了上述所提到的通訊系統。電路中利用共閘極與共源極架構消除雜訊，使用PMOS閘極控制偏壓當作頻段的選擇方式，低頻段與高頻段所消耗的功率分別為34.2 mW與34.6 mW，晶片面積為0.35 mm2。
接收機前端電路，包括低雜訊放大器、混頻器、除頻器。射頻前端電路接續低雜訊放大器的設計概念，配合兩組混頻器將射頻訊號降到基頻，並產生四種相位輸出，混頻器的本地振盪頻率由除頻器所提供。此除頻器為除二且輸出可以產生四種相位，使用除頻器輸入頻率為射頻訊號的兩倍，輸出即可供應兩組混頻器所需之本地振盪頻率。接收機前端電路分高、低頻段，消耗功率分別為58.5 mW與58.9 mW，晶片面積為0.6 mm2。
本論文中提出一種振盪器架構-變壓器混合內插式壓控振盪器，改善振盪器頻寬的限制，完成較寬頻的振盪器，此電路功率消耗為1.03 mW，晶片面積為0.5 mm2。

This thesis presents the design of a low noise amplifier for wireless communication standard applications including GSM, GPS, WCDMA, IEEE 802.11b/g, UWB group-1, and WiFi in UMC 90nm 9-metal-single-poly CMOS process. In software defined radio systems, the communication protocol to be used by in mobile devices is selected by software’s. Therefore, there are two frequency bands in the low noise amplifier we designed, which range from 0.8 GHz to 2.4 GHz(low frequency band) and from 3 GHz to 6 GHz(high frequency band), respectively. The band selection controlled by the gate bias voltage. The power consumption of the low and high frequency bands are 34.2 mW and 34.6 mW, respectively. The chip area is 0.35 mm2.
The receiver front-end circuit in this thesis includes a low noise amplifier, two mixers, and a frequency divider. The low noise amplifiers we designed is connected to two mixers, which down convert the RF signal to a medium frequency signal, and generate quadrature signals at the output. The local oscillation frequency for the mixers is provided by a divider, which is a quadrature output divide-by-two divider. The divider can provide LO signals to the mixers by injecting a signal that has twice the frequency the mixers need at the input of the divider. The receiver front-end circuit also has two modes, high and low frequency mode. The power consumption of two modes are 58.5 mW and 58.9 mW, respectively. The chip area is 0.6 mm2.
In addition, This thesis also presents the design of a new oscillator architecture: Transformer hybrid interpolative VCO. This VCO improves the oscillator bandwidth constraints, and completes broader band oscillators. The power consumption of the VCO is 1.03 mW, and a chip area of 0.5 mm2.

CH1
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CH2
[1] A. Ismail and A. Abidi, “A 3-10-GHz low-noise amplifier with wideband LC-ladder matching network,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2269–2277, Dec. 2004.
[2] F. Bruccoleri, E. M. Klumperink, and B. Nauta, “Wide-band CMOS low-noise amplifier exploiting thermal noise canceling,” IEEE J. Solid-State Circuits, vol. 39, no. 2, pp. 275–282, Feb. 2004.
[3] Bagheri, R.; Mirzaei, A.; Chehrazi, S.; Heidari, M. E.; Lee, M.; Mikhemar, M.; Tang, W.; Abidi, A. A.; “An 800-MHz–6-GHz Software-Defined Wireless Receiver in 90-nm CMOS” in IEEE JNL 2006 Dig.
[4] Sanghyun Woo, Woonyun Kim, Chang-Ho Lee, Kyutae Lim, Joy Laskar, “A 3.6mW differential common-gate CMOS LNA with positive-negative feedback,” Solid-State Circuits Conference - Digest of Technical Papers, Feb. 2009 .
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CH3
[1] A. Ismail and A. Abidi, “A 3-10-GHz low-noise amplifier with wideband LC-ladder matching network,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2269–2277, Dec. 2004.
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[3] Bagheri, R.; Mirzaei, A.; Chehrazi, S.; Heidari, M. E.; Lee, M.; Mikhemar, M.; Tang, W.; Abidi, A. A.; “An 800-MHz–6-GHz Software-Defined Wireless Receiver in 90-nm CMOS” in IEEE JNL 2006 Dig.
[4] Camus, M., Butaye, B., Garcia, L., Sie, M., Pellat, B., Parra, T., “A 5.4mW 0.07mm2 2.4GHz Front-End Receiver in 90nm CMOS for IEEE 802.15.4 WPAN” ,Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International, pp. 368-620. 2008.
[5] Koli, K., Kallioinen, S., Jussila, J., Sivonen, P., Parssinen, A., “A 900-MHz Direct Delta-Sigma Receiver in 65-nm CMOS,” Solid-State Circuits, IEEE Journal of, Dec. 2010.
[6] Hermann, C., Miinker, C., Klar, H., “A transformer based 1.8 – 1.9GHz low-IF receiver for 1V in 0.13μm CMOS, ” Radio Frequency Integrated Circuits (RFIC) Symposium, 2006.
[7] Hong Zhang, Guican Chen, Xiao Yang, “Fully Differential CMOS LNA and Down-Conversion Mixer for 3 to 5 GHz MB-OFDM UWB Receiver” ,RFIT2007-IEEE International Workshop on Radio-Frequency Integration Technology, Dec. 9-11, 2007, Singapor.
[8] Yun-A Shim, Jeongseon Lee, Sek-Kyun Han, Sang-Gug Lee, “Low Noise RF Front-End Receiver for 3~5 GHz UWB” , Advanced Communication Technology, 2008. ICACT 2008. 10th International Conference on.
[9] A. Bevilacqua, A. Vallese, C. Sandner, M. Tiebout, A. Gerosa, and A. Neviani, “A 0.13μm CMOS LNA with integrated balun and notch filter for 3-to-5GHz UWB receivers” ,in IEEE ISSCC Digest of Technical Papers, San Francisco, CA, Feb 2007, pp. 420–421.
[10] G. Sapone, G. Palmisano, “ A Low-Power 3-5-GHz UWB Down-Converter with
Resistive-Feedback LNA in a 90-nm CMOS Proces” Microwave Integrated Circuit Conference, 2008. EuMIC 2008. European.

CH4
[1] B. Razavi, design of analog CMOS Intergrated Circiuts, McGraw Hill, 2001.
[2] B. Razavi, RF Microelectornics, PRENTICE HALL PTR, 1998, pp.231-233.
[3] Michael Mark, Jan M. Rabaey, “A 13.2 mW 1.9 GHz interpolative BAW-based VCO for miniaturized RF frequency synthesis,” Circuits and Systems, 2009. ISCAS 2009.
[4] Shih-An Yu, Chin-Chun Meng, Shey-Shi Lu, “A 5.7 GHz interpolative VCO using InGaP/GaAs HBT technology,” IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 12, NO. 2, FEBRUARY 2002.
[5] Li, Z. and K. O. Kenneth, “A low-phase-noise and low-power multiband CMOS voltage-controlled oscillator,” IEEE J. Solid-State Circuits, Vol. 40, No. 6, 1296–1302, Jun. 2005.
[6] J. Kim, J. Plouchart, N. Zamdmer, M.Cherony, Y. Tan, M. Yoon, R. Trzcinski, M. Talbi, J. Safran, A. Ray, and L. Wagner, “A power optimized widely-tunable 5-GHZ monolithic VCO in a digital SOI CMOS technology on high resistivity substrate,” in Proc. ISLPED, Aug 2003, pp. 434---439.