近年來科技的快速發展帶動人們對於各類型消費性電子產品的需求急遽提升，傳統的嵌入式記憶體逐漸面臨到物理尺寸的限制以及能耗的增長等嚴峻的挑戰。因此目前有許多新型態的非揮發式記憶體被開發出來以解決這些問題，其中自旋轉移矩磁阻式記憶體被視為目前最有潛力可以取代傳統記憶體的新興記憶體，它具有快速的讀寫速度、良好的儲存密度、極低的漏電功率以及優異的耐用性等優點。然而由於其物理結構和內在特性的影響，自旋轉移矩磁阻式記憶體在使用的過程中可能會發生永久性的故障或是暫時性的錯誤，導致自旋轉移矩磁阻式記憶體系統的可靠度降低。
有鑒於此，本篇論文針對了自旋轉移矩磁阻式記憶體的可靠度問題提出了協同式錯誤修正碼技術，該技術主要包含基於正交拉丁方陣碼建構的錯誤修正碼以及寫後驗證操作兩部分，使記憶體系統能夠容忍線上使用時產生的永久性錯誤以及暫時性錯誤。基於正交拉丁方陣碼建構的錯誤修正碼具有低編解碼時間以及低面積成本的優點，能夠在提升自旋轉移矩磁阻式記憶體可靠度的同時，協助其保持快速的讀寫速度和良好的儲存密度；寫後驗證操作能夠在記憶體系統寫入資料時產生額外的保護資訊，這些保護資訊能夠在錯誤修正碼進行解碼之前先行消除一部分或是全部的永久性故障，減少錯誤數量超過錯誤修正碼保護能力的情形，進一步提升自旋轉移矩磁阻式記憶體系統的可靠度。
本論文實現了協同式錯誤修正碼技術所需的硬體電路，並利用Matlab進行可靠度與壽命模型的推導與模擬。實驗結果顯示1 GB 大小的STT-MRAM 配備保護能力為二的協同式錯誤修正碼技術可在系統運行十萬小時後保有 99.9 % 的可靠度；配備保護能力為三的協同式錯誤修正碼技術可在系統運行百萬小時後保有 99.8 % 的可靠度。電路模擬結果顯示額外增加的硬體成本約為3%。

In recent years, the rapid development of fabrication technology has driven demands for various electronics products. However, traditional embedded memories are facing many severe challenges such as physical size limitations and increased energy consumption. Therefore, many new types of non-volatile memories have been developped to solve these problems. Among them, spin-transfer torque magnetoresistive random access memory (STT-MRAM) is considered as the most promising emerging memory and is the best candidate for replacing traditional memory. It has the advantages of fast read and write speed, high storage density, extremely low leakage power, and outstanding durability. However, due to the influences of its physical structure and inherent characteristics, STT-MRAM suffers from permanent faults or temporary errors during online usage. The reliability of STT-MRAM is thus significantly threatened.
To cure this dilemma, the synergistic error correction code technique is proposed in this thesis to deal with the reliability issue of STT-MRAM. It mainly includes two phases: error correction code based on orthogonal Latin square (OLS) codes and the verify-after-write operations, which enable the memory system to tolerate permanent and temporary errors. The error correction code based on OLS codes has the advantages of lower encoding and decoding latencies and less area cost. It can enhance the reliability of STT-MRAM while maintaining faster read/write speeds and higher storage density. The verify-after-write operations generate additional information for protection after the write cycles. The stored syndrome information can help to deactivate the effects of permanent errors before the codeword is decoded. Therefore, the probability of errors exceeding the protection capacity of the adopted error correction code is greatly reduced. The reliability of STT-MRAM thus can be raised significantly.
We have also implemented the hardware architecture of the proposed synergistic error correction code technique. Experimental results show that for a 1-GB STT-MRAM equipped with the protection capability of two can maintain 99.9% reliability after 105 operation hours. When the protection capability is three, 99.8% reliability can be maintained after 106 operation hours. The additional hardware cost is about 3%.

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