本論文提出了一種用於LEO衛星通信的27-31 GHz 七位元數位控制向量合成相移器， 此晶片採用台積電 90 奈米 CMOS製程。相移器由正交全通濾波器（QAF）和由一八位元電流數位類比轉換器（IDAC）偏流的類比差動加法器組成，其中透過八位元電流數位類比轉換器控制類比加法器的電流以及兩位元的象限選擇，使最小位元可以產生2.8125度相移，最後產生從0到360°的相移。本論文藉由正交全通濾波器和類比加法器的級間匹配優化後，可最大程度地減少系統損耗，因此與其他主動式相移器相比，此相移器能夠以更低的功耗實現更高的增益。此相移器 128 個相移狀態是從八位元IDAC和兩位元象限選擇生成的 1024 個相移狀態中選取， 因此本電路可以實現更低均方根相位誤差。根據測量結果，相移器的RMS相位誤差為0.18°至0.21°，RMS振幅誤差為0.68至0.9 dB。在27-31 GHz頻段內，平均增益為-1.36至0.13 dB。晶片核心尺寸為 0.63 mm2。相移器在1.2 V供應電壓下總功耗為10mW。

This paper presents a 27-31GHz 7-bit digital control vector-sum phase shifter for LEO satellite communications transmitter which is fabricated in a 90-nm CMOS process. The phase shifter consists of a quadrature all-pass filter (QAF) and an analog vector adder. The inter-stage matching work is designed between QAF and the analog differential adder to minimize the insertion loss and the analog differential adder that is biased with an 8-bit current digital-to-analog converter (IDAC), where the IDAC is used to control the bias current of the analog adder so that the phase shift from 0 to 360° can be generated in steps of 2.8°. The 128 phase shift states of this phase shifter are selected from the 1024 phase shift states generated by the 8-bit IDAC and 2-bit quadrant selection so that this circuit can achieve lower RMS phase error. Over the band of interest, the phase shifter achieves the average gain of 0.13 ~ -1.36 dB. The RMS amplitude error of 0.68 ~ 0.9 dB and the RMS phase error of 0.18 ~ 0.21°. The output P1dB is -1 ~ -7.5 dBm over 27-31 GHz. Consuming the power of 10 mW with 1.2 V supply voltage. The chip core area is 0.63 mm2 .

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