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研究生: 徐偉豪
Wei-Hao Hsu
論文名稱: 以FPGA 實現電源供應器測試設備之可編程電子負載同步控制器的設計與應用
To apply FPGA on the design and application of the synchronous controller of programmable electronic load which tests the equipment of power supply
指導教授: 徐敬文
Ching-Wen Hsu
黃進芳
Jin-Fung Huang
口試委員: 張勝良
Sheng-Lyang Jang
劉榮宜
Ron-Yi Liu
陳國龍
Kuo-Lung Chen
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2007
畢業學年度: 95
語文別: 中文
論文頁數: 109
中文關鍵詞: FPGA電子負載電源供應器
外文關鍵詞: FPGA, electronic load, power supply
相關次數: 點閱:260下載:5
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目前電子測試儀器產業界對於可編程電子負載主要分類直流可編程電子負載、交
流可編程電子負載、交直流可編程電子負載,其中以直流可編程電子負載的種類居
多。其原因不外乎電子消費性產品所使用的絕大多數是以直流電壓作為電源供應器,
所出現的產品大致可分類切換式電源供應器、電池、太陽能電池、燃料電池等等,這
些電源產品於研發及生產過程中都需要進行特定的測試才能確保使用者的安全。
本篇論文主要的研究內容為利用可程式邏輯陣列(FPGA)來設計適合於需求同步
控制多通道可編程電子負載的控制器,由於可編程電子負載於特定的工作模式下(定
電壓模式(CC MODE)、定電流模式(CV MODE)、定電阻模式(CR MODE)等等)需要
多組同時控制的控制點,所以以往採用軟體搭載CPU 的控制方式需求為較緩慢的控
制與為較難以掌控的多模組同步問題。故,期望本論文可以利用可程式邏輯陣列
(FPGA)設計的控制器來實現多模組可編程電子負載控制及同步問題。並且提供高速
的動態負載。
在論文中,介紹可編程電子負載的基本原理、基本運用、功能、電路架構及其分
析、控制器(FPGA)控制方式、控制器(FPGA)通訊及暫存器格式、控制器(FPGA)
設計架構及其方法)…等等。
在設計初期,將先建立起可編程電子負載基礎模組--定電流模組,在此稱之為功
率級(Power Stage)。往後的各個操作功能都是利用此基礎模組進行定電流模式控制,
以達到等效模擬定電壓、定電阻等等功能。
最後,在實做的成果證明了,以硬體控制的設計方式比軟體控制的設計在同步控
制上更為精確。


Currently, the industry of electronic testing instruments classifies programmable electronic load into DC programmable electronic load, AC programmable electronic load and AC/DC programmable electronic load. Products related to DC programmable electronic load have the biggest share in terms of the variety of product offerings and the volume. The main reason is that most consuming electronic products use direct current as power source. Most common types of these products are switching power supply, batteries,solar batteries and fuel batteries. These main power products require several specific
testing in the R&D and production process to ensure consumers’ safety.
The main topic of this research paper is to design controller appropriate for programmable electronic load, by applying FPGA. Under certain operation modes (e.g. CC mode, CV mode, and CR mode etc), programmable electronic load needs multiple simultaneously-controlled points. The current control mechanism is to have software attached to CPU. Such an approach would cause slower processing speed and unexpected synchronization problems. This paper is expected to use FPGA-designed controller to solve the issues around programmable mutli-channel electronic load and synchronization
while providing dynamic load at higher speed.
In this paper, we cover the basic principles, basic applications, functionalities, circuit structure & analysis, FPGA controlling mechanism, FPGA formats for communication and register, and FPGA design structure and control points of the programmable electronic load.
programmable electronic load.
Before conducting the experiment, we will first establish the basic module of power stage. Functionalities introduced in the paper are built upon this basic module on cc mode,in order to provide the benefits of cv mode and cr mode.
The research results demonstrate that the control-mechanism via hardware can
provide more precision in synchronization than that via software.

目 錄 中文摘要 -------------------------------------------------------------------I 英文摘要 -------------------------------------------------------------------II 圖表索引 -------------------------------------------------------------------IV 第一章 緒論 ----------------------------------------------------------------1 1.1 研究動機 ---------------------------------------------------------------1 1.2 研究重點 ---------------------------------------------------------------1 1.3 研究方法 ---------------------------------------------------------------2 1.4 論文架構和概觀 ---------------------------------------------------------3 第二章 可編程電子負載工作模式探討 ------------------------------------------4 2.1 可編程電子負載系統方塊圖 -----------------------------------------------4 2.2 靜態定電流操作模式/ 動態定電流操作模式 ---------------------------------5 2.3 靜態定電壓操作模式 -----------------------------------------------------6 2.4 靜態定電阻操作模式 -----------------------------------------------------8 第三章 可編程電子負載控制電路探討 ------------------------------------------10 3.1 功率級( Power Stage )控制電路 ------------------------------------------10 3.2 定電流模式(CC MODE)控制電路 --------------------------------------------14 3.3 定電壓模式(CV MODE)控制電路 --------------------------------------------17 3.4 定電阻模式(CR MODE)控制電路 --------------------------------------------20 3.5 電流上昇下降斜率(Current Slew Rate)控制電路 ----------------------------22 3.6 電壓取樣參考信號源 -----------------------------------------------------23 3.7 電流取樣( Isense)參考信號源 --------------------------------------------24 第四章 準確度校驗需求程序 --------------------------------------------------25 4.1 準確度校驗方式----------------------------------------------------------27 4.2 校驗需求的各點與斜率(Slew Rate)及偏移量(Offset)關係---------------------28 第五章 以FPGA 實現可編程電子負載的同步並聯控制控制器------------------------29 5.1 控制系統架構圖----------------------------------------------------------32 5.1.1 可編程電子負載控制器的FPGA 架構拆解-----------------------------------32 5.1.2 控制器FPGA 於可編程電子負載中控制功能---------------------------------33 5.1.3 可編程電子負載控制器FPGA 單元設計目的---------------------------------35 5.2 控制方式、控制命令定義--------------------------------------------------37 5.2.1 控制方式--------------------------------------------------------------37 5.2.2 控制命令定義----------------------------------------------------------41 5.2.3 FPGA I/O 控制信號定義-------------------------------------------------42 5.3 可編程電子負載控制器功能方塊設計----------------------------------------46 5.3.1 控制器之8051 Interface Control Block----------------------------------46 5.3.2 控制器之Decoder Block-------------------------------------------------49 5.3.3 控制器之Byte to Word Control Block------------------------------------51 5.3.4 控制器之Command Buffer Block------------------------------------------54 5.3.5 控制器之Address Control Block-----------------------------------------55 5.3.6 控制器之Dual Port Ram Control Block-----------------------------------57 5.3.7 控制器之Clock Generator Block ----------------------------------------59 5.3.8 控制器之Transient Control Block---------------------------------------61 5.3.9 控制器之Digital to Analog Control Block-------------------------------63 5.3.10 控制器之Slew Rate Digital to Analog Control Block--------------------65 5.3.11 控制器之Status Command Block-----------------------------------------67 5.4 FPGA 同步並聯控制控制器整合---------------------------------------------69 5.4.1 控制器整合結果--------------------------------------------------------69 5.4.2 靜態操作模式-主副控設定方式-------------------------------------------70 5.4.3 動態操作模式-主副控設定方式-------------------------------------------82 5.4.4 自動執行程序(Auto 自動執行程序(Auto Run Program)) 操作模式-主副控設定方式-----------------------------------------------------92 第六章 實做成果-------------------------------------------------------------98 6.1 實做組成介紹------------------------------------------------------------98 6.1.1 散熱片與風扇----------------------------------------------------------98 6.1.2 功率級(Power Stage) 電路版--------------------------------------------98 6.1.3 可編程電子負載功能控制電路版------------------------------------------99 6.2 實做PCB 成果------------------------------------------------------------99 6.2.1 實做PCB 樣品組裝------------------------------------------------------99 6.3 實做成果測試波形--------------------------------------------------------100 6.3.1 定電流模式(CC MODE)控制電路-------------------------------------------101 6.3.2 定電壓模式(CV MODE)控制電路-------------------------------------------101 6.3.3 定電阻模式(CR MODE)控制電路-------------------------------------------101 6.3.4 電流上昇下降斜率(Current Slew Rate)控制電路---------------------------102 6.3.5 靜態設定變更實做成果測試波形------------------------------------------102 6.3.6 動態操作實做成果測試波形----------------------------------------------103 6.3.7 單組負載模組以外部同步控制信號進行電流設定成果測 試波形----------------------------------------------------------------------104 6.3.8 雙組負載模組以外部同步控制信號進行電流設定成果測 試波形----------------------------------------------------------------------105 第七章 總結-----------------------------------------------------------------107 7.1 結論--------------------------------------------------------------------107 7.2 未來研究方向------------------------------------------------------------107 參考文獻 -------------------------------------------------------------------108

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