與現今廣泛應用在無線通訊系統中的正交分頻多工(OFDM)技術相比，廣義分頻多工(GFDM)有較高的頻譜效率，較低的帶外輻射功率，對載波頻率偏移有較高的抗性等優點。除此之外，GFDM調變技術擁有高度的彈性與可調適性，可以透過改變調變資料的結構來符合不同應用的需求，因此，綜合以上原因，GFDM便被討論為5G的調變候選技術之一。
在GFDM接收器中，聯合最小均方誤差(joint-MMSE)接收器擁有最好的BER效能表現，而其運算複雜度也是最高，當系統參數需求較大時會造成過大系統複雜度的問題。近年來基於矩陣分解方式的joint-MMSE GFDM接收器演算法利用離散傅立葉轉換(DFT)矩陣化簡了矩陣運算的複雜度，使得joint-MMSE GFDM接收器電路設計與實現更值得被研究與探討。
本論文將基於超大型積體電路設計與實現joint-MMSE GFDM接收器電路。其中，我們在設計實現上加入快速傅立葉轉換(FFT)演算法位元反轉的考量，並提出一個新的joint-MMSE GFDM接收器資料處理流程，在電路架構設計上利用分時多工架構以達成低複雜度之目的。此外，針對系統中記憶體讀寫過程，我們提出一個避免資料遺失的記憶體位址存取方法。在本論文中的設計使用台積電90奈米製程下實現，根據合成結果顯示，在工作頻率204 MHz下，使用了492.6k個邏輯閘。在我們提出的資料排序合併處理策略下，我們的設計可以減少約16%的面積花費。另外，與目前所知FPGA實現結果相比，本論文的設計達成了低邏輯閘數並且具備可調適性的電路結果。

This thesis presents the configurable and low-complexity VLSI architecture of joint minimum mean square error generalized frequency division multiplexing (joint-MMSE GFDM) receiver. First of all, we consider the bit reverse permutation caused from FFT algorithm and then propose a new joint-MMSE GFDM data processing flow. In proposed data processing flow, the additional circuit and latency to solve bit reverse problem is significantly reduced. Moreover, the time sharing architecture and radix-2 SDF FFT architecture are adopted in our design to reduce hardware complexity. For high flexible requirement of GFDM, every processing element in system is design for supporting different system parameters setting. Furthermore, a memory address access algorithm for avoiding data loss is proposed for the memory reading and writing process in the proposed system. Proposed design is synthesized based on TSMC 90nm technology. At 204 MHz operating frequency, proposed architecture uses 492.6 kGEs. The area cost is reduced about 16% by our data permutation strategy. Moreover, the proposed design can achieve low area complexity compared to the FPGA implementation from other work as we know.

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