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研究生： 莊育錚
Yu-Cheng Chuang
論文名稱： 應用3D電感之電容耦合注入鎖定除頻器設計與除三注入鎖定除頻器頻率調動之研究
Design of Capacitive Cross-coupled Injection-Locked Frequency Divider with 3D Inductor and Frequency Tuning in ÷3 Cross-Coupled Injection-Locked Frequency Divider
指導教授： 張勝良
Sheng-Lyang Jang
徐敬文
Ching-Wen Hsue
口試委員: 黃進芳
Jhin-Fang Huang
賴文政
Wen-Cheng Lai
學位類別： 碩士
Master
系所名稱： 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年： 2016
畢業學年度： 104
語文別： 英文
論文頁數： 138
中文關鍵詞： 壓控振盪器 、注入鎖定除頻器
外文關鍵詞： VCO, ILFD
相關次數： 點閱：190  下載：0 
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    • 本篇論文提出了三顆不同結構的注入鎖定除頻器，分別為三共振除四注入鎖定除頻器、應用3D電感之除二注入鎖定除頻器以及寬除頻範圍除三注入鎖定除頻器。
    首先，第一部分使用台積電矽鍺0.18微米製程，來呈現三共振除四注入鎖定除頻器。此除頻器的設計方式是用交叉耦合(cross couple)結合單注入MOSFET與RLC共振腔。於兩可變電容連接處加上電阻，增加其鎖頻範圍。當工作電壓操作在1伏特，注入訊號強度為0dBm時，可得注入鎖定頻帶為9.9~13 GHz，除頻比例為27.07%。此晶片的核心功率消耗為7.2 mW，晶片面積為0.83×1.06 mm2。
    其次，我們使用台積電0.18微米製程，來呈現低功耗高鎖頻範圍，應用3D電感之除二注入鎖定除頻器。此除頻器設計則是基於一電容耦合的壓控振盪器，加上一個MOSFET做為訊號注入，並使用3D電感來節省晶片面積。當工作電壓操作在0.8伏特，注入訊號強度為0dBm時，可得注入鎖定頻帶為1.5~9.5 GHz，除頻比例為145.4%。此晶片的核心功率消耗為10.6 mW，晶片面積為0.87×0.705 mm2。
    最後，我們探討一個使用台積電0.18微米製程之寬除頻範圍之除三注入鎖定除頻器的頻率變化。此除頻器使用兩個MOSFETs做注入，加上一組雙頻RLC共振腔。當工作電壓操作在1伏特，注入訊號強度為0dBm時，可得注入鎖定頻帶為6.9~11.9 GHz，除頻比例為53.19%。此晶片的核心功率消耗為5.6 mW，調動Vtune量測頻率變化有發現遲滯現象，但不影響鎖頻範圍，晶片面積為0.915×0.962 mm2。

    In this thesis, we propose three different kinds of injection-locked frequency dividers (ILFD): triple bands divide-by-4 ILFD, ultra-wide-locking-range divide-by-2 ILFD with 3D inductor and dual bands divide-by-3 ILFD, respectively.
    First, a wide locking range divide-by-4 ILFD is implemented in the TSMC SiGe 0.18 μm BiCMOS process. The ILFD is based on a cross-coupled oscillator with a direct injection MOSFET and a RLC resonator. Resistors are used to enhance the locking range. At the drain-source bias of 1V, and at the incident power of 0 dBm the locking range of the divide-by-4 ILFD is 3.1 GHz, from the incident frequency 9.9 to 13.0 GHz, the locking range percentage is 27.07%. The power consumption of ILFD core is 7.2mW. The die area is 0.83 × 1.06 mm2.
    Secondly, we present a lower power and wide locking range divide-by-2 with capacitive cross-coupled injection-locked frequency divider (ILFD) implemented in the TSMC standard 0.18 μm CMOS process. The ILFD is based on a capacitive cross-coupled VCO with one injection MOSFET for coupling the external signal to the resonator. The ILFD uses two 3-dimensional inductors to reduce the die area. At the supply voltage of 0.8V, the divider’s free-running frequency is 1.89 GHz, and at the incident power of 0 dBm the locking range is about 8 GHz (145.4%) from 1.5 to 9.5GHz. The core power consumption is 10.6mW. The die area is 0.87×0.705 mm2.
    Finally, we study the RF performance of a wide locking range divide-by-3 injection-locked frequency divider (ILFD) in CMOS process. The ILFD circuit bases on capacitive cross-coupled oscillator and uses dual-resonance RLC resonator. The power consumption of the ILFD core is 5.5mW and the locking range is from 6.9 to 11.9 GHz (53.2%) at injection power Pinj=0dBm. Measured tuning range depends upon the direction of voltage tuning, the tuning range shows a hysteresis loop, which does not affect on the locking range of ILFD. The die area is 0.915×0.962 mm2.

    中文摘要 I Abstract III 誌謝 V Table of Contents VI List of Figure IX Chapter 1 Introduction 1 1.1 Background 1 1.2 Thesis Organization 4 Chapter 2 Overview of Voltage-Controlled Oscillators 6 2.1 Introduction 6 2.2 Design Concepts of Voltage-Controlled Oscillator 6 2.2.1 Parameters of a Voltage-Controlled Oscillator 7 2.2.2 Phase Noise 9 2.2.3 Quality Factor 14 2.3 Basic Theory of Oscillators 16 2.3.1 Two-Port (Feedback) View 16 2.3.2 One-Port (Negative Resistance) View 18 2.4 Classification of Oscillators 20 2.4.1 Ring Oscillator 20 2.4.2 LC-Tank Oscillator 25 2.5 Type of the LC Oscillator 29 2.5.1 Single Transistor Oscillator 30 2.5.2 One-Port Oscillator (Negative-Gm Oscillator) 33 2.5.3 Cross-Coupled Oscillator 37 2.5.4 Complementary Cross-Coupled Topology 39 2.6 Research in RLC-Tank 42 2.6.1 Resistors 43 2.6.2 Inductor 44 2.6.3 Transformer 50 2.6.4 Capacitors 55 2.6.5 Varactors 57 Chapter 3 Overview of Injection Locking Frequency Divider 63 3.1 Introduction 63 3.2 Principle of Injection Locked Frequency Divider 64 3.3 Locking Range 66 Chapter 4 Triple-Resonance Divide-by-4 Injection-Locked Frequency Divider 69 4.1 Introduction 69 4.2 Circuit Design 70 4.3 Measurement Results 72 Chapter 5 Capacitive Cross-Coupled Injection-Locked Frequency Divider with 3D Inductor 84 5.1 Introduction 84 5.2 Circuit Design 86 5.3 Measurement Results 88 Chapter 6 Frequency Tuning in ÷3 Cross-Coupled Injection-Locked Frequency Divider 97 6.1 Introduction 97 6.2 Circuit Design 98 6.3 Measurement Results I 101 6.4 Measurement Results II 105 Chapter 7 Conclusions 113 References 114

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