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研究生： 許劍銘
Chien-Ming Hsu
論文名稱： 可調式Gm-C迴路濾波器的高性能頻率合成器晶片設計
Chip Design of High Performance Frequency Synthesizers with the Tunable Gm-C Loop Filter
指導教授： 黃進芳
Jhin-Fang Huang
劉榮宜
Ron-Yi Liu
口試委員: 徐敬文
Ching-Wen Hsue
張勝良
Sheng-Lyang Jang
陳國龍
Kuo-long Chen
學位類別： 碩士
Master
系所名稱： 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年： 2012
畢業學年度： 100
語文別： 英文
論文頁數： 164
中文關鍵詞： 頻率合成器 、迴路濾波器 、分數型 、整數型
外文關鍵詞： Loop filter, PLL, Frequency synthesizer, Gm-C
相關次數： 點閱：303  下載：5 
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  •  上一筆

    • 近年來，以鎖相迴路為主的頻率合成器大量被使用在無線通訊系統中。相對地，各式各樣的頻率合成器就被研發出來。在本篇論文中，設計了兩個可調式的Gm-C迴路濾波器頻率合成器，可調式的Gm-C迴路濾波器可以取代被動濾波器，來改善製程變異對電阻、電容的影響並可以有效的減少面積消耗。
    第一顆晶片是21.6 GHz低功耗整數型頻率合成器，此電路電壓控制振盪器採用全nMOS考畢子架構來獲得低相位雜訊的性能，並使用注入鎖定除頻器為第一級除頻電路，因此功率消耗能夠被大大的減少，此頻率合成器使用台積電所提供90奈米CMOS製程以1.2伏特來完成晶片研製與量測。量測結果顯示頻率鎖定於21.6 GHz時，距離主頻1MHz處的相位雜訊為 -103.3 dBc/Hz晶片面積包含pads為0.925 mm2，總消耗功率為9.54 mW。
    第二顆晶片是5.8 GHz分數型頻率合成器，主要是利用了三角積分調變器去實現分數的除數，而三角積分調變器可將量化雜訊移往高頻，再藉由鎖相迴路中迴路頻寬的特色將雜訊濾除，並使用考畢子振盪器、平均電容、動態充電泵來降低電路的相位雜訊，此頻率合成器使用台積電所提供0.18微米CMOS製程以1.8伏特來完成晶片研製與量測。量測結果顯示頻率鎖定於5.8GHz時，距離主頻1MHz處的相位雜訊為 -109.8 dBc/Hz晶片面積包含pads為1.032 mm2，總消耗功率為22.7 mW。

    Recently, the PLL-based frequency synthesizers are widely used in wireless communication systems; however, many of PLL architectures are created. This thesis is a design of two chips of frequency synthesizer with tunable Gm-C loop filter. The tunable Gm-C loop filter, instead of a conventional passive loop filter, is used to overcome the process variations of resistance (R) and capacitance (C).

    The first chip, a 21.6 GHz low-power integer-N frequency synthesizer, is implemented in TSMC 90 nm CMOS process. In this proposed circuit, there are two important features. The primary advantage is the use of an all-nMOS cross-coupled Colpitts VCO, which decreases transistor parasitic capacitances and reduces phase noise. Second, an injection-locked frequency divider (ILFD) is inserted in the first divider stage to divide the high frequency signal. At low supply voltage of 1.2-V, the chip’s measured results achieved locked output frequency tunable from 21.54~21.96 GHz and the phase noise is -103.3 dBc/Hz at 1MHz offset at 21.6 GHz. The overall power consumption is 9.54 mW. Including pads, the chip area is 0.925 (0.925 × 1.0) mm2.

    The second chip, a 5.8 GHz fractional-N frequency synthesizer, is fabricated in TSMC 0.18 mm CMOS process. To improve phase noise, the VCO adopts cross-coupled Colpitts structure and uses average varactor. The CP employs dynamic current-matching circuit to compensate for the channel-length modulation effect. Furthermore, the MASH 1-1-1 modulator, which performs the fractional division number, can improve the phase noise as well. In this chip design, the measured results achieve locked output frequency tunable from 5.56~5.95 GHz and the phase noise is -109.8 dBc/Hz@1M at 5.8 GHz. The overall power consumption is 22.7 mW. Including pads, the chip area is 1.032 (1.2 × 0.86) mm2.

    Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Focus and Contributions 2 1.3 Organization of This Thesis 2 Chapter 2 PLL-Based Frequency Synthesizers 5 2.1 Wireless Transceiver 5 2.2 Phase-Locked Loop 6 2.2.1 Integer-N Frequency Synthesizer 7 2.2.2 Fraction-N Frequency synthesizer 8 2.3 Building Blocks of Frequency Synthesizer 9 2.3.1 Voltage-Controlled Oscillator (VCO) 9 2.3.2 Phase Frequency Detector Circuit (PFD) 10 2.3.3 Charge Pump Circuit (CP) 13 2.3.4 Loop Filter 13 2.3.5 Frequency Divider 14 2.4 Loop Filter Design 15 2.4.1 First-Order Loop Filter 15 2.4.2 Second-Order Loop Filter 16 2.4.3 Third-Order Loop Filter 19 2.5 Figures of Merit of a Frequency Synthesizer 20 2.5.1 Jitter 20 2.5.2 Phase Noise 21 2.5.3 Spurs 22 2.6 Frequency Synthesizer Paper Survey 23 2.7 Summary 35 Chapter 3 PLL Circuits Design 37 3.1 Voltage-Controlled Oscillator Circuit (VCO) 37 3.1.1 Operation Principle of Oscillator 38 3.1.2 Ring Oscillator 39 3.1.3 LC-Tank VCO Circuit 40 3.1.4 Passive Components in LC-Tank VCO 43 3.1.5 Switched-Capacitors VCO 49 3.2. Frequency Divider 50 3.2.1 Multi-Modulus Divider 50 3.2.2 CML Divider and TSPC Divider 51 3.3 S-D Modulator 52 3.3.1 1st-Order S-D Modulator 52 3.3.1 Higher-Order S-D Modulator 55 3.4 Tunable Gm-C Loop Filter 57 3.4.1 Resistor Equivalent Circuit 58 3.4.2 Inductor Equivalent Circuit 59 3.5 Summary 60 Chapter 4 A 21.6 GHz Integer-N Frequency Synthesizer with Tunable Gm-C loop Filter Chip Design 61 4.1 Introduction 61 4.2 System Block Diagram 64 4.3 Building Block and Simulation 65 4.3.1 Voltage-Controlled Oscillator (VCO) 65 4.3.2 Injection-Locked Frequency Divider (ILFD) 67 4.3.3 Frequency and Phase Detector (PFD) 69 4.3.4 Charge Pump (CP) 71 4.3.5 Programmable Divider Circuit 72 4.3.6 Tunable Gm-C Loop Filter 77 4.3.7 Overall System Simulation Results 82 4.4 Chip Measurements 84 4.4.1 RF Chip Layout Considerations 84 4.4.2 RF Chip Measurement Considerations 85 4.4.3 Chip Floor Plan and PCB Design 85 4.4.4 Test Environment Setup 87 4.4.5 Measured results 88 4.4.6 Specifications and Performance Comparison 90 4.5 Summary 92 Chapter 5 A 5.8 GHz Fractional-N Frequency Synthesizer with Tunable Gm-C Loop Filter Chip Design 93 5.1 Introduction 93 5.2 System Block Diagram 94 5.3 Building Block and Simulation 95 5.3.1 Voltage-Controlled Oscillator (VCO) 95 5.3.2 Frequency and Phase Detector (PFD) 98 5.3.3 Charge Pump (CP) 99 5.3.4 Programmable Divider 101 5.3.5 MASH 1-1-1 S-D Modulator 106 5.3.6 Tunable Gm-C Loop Filter 109 5.3.7 The Overall PLL System Simulation Results 113 5.4 Frequency Synthesizer Chip Measurements 114 5.4.1 Chip Floor Plan and PCB Design 115 5.4.2 Test Environment Setup 116 5.4.3 Measurement Results 117 5.5 Specifications and Performance Comparison 120 5.6 Summary 122 Chapter 6 Conclusions and Future Work 123 6.1 Conclusions 123 6.1.1 Chip1: A 21.6 GHz Integer-N Frequency Synthesizer with Tunable Gm-C loop Filter 123 6.1.2 Chip2: A 5.8 GHz Fractional-N Frequency Synthesizer with Tunable Gm-C Loop Filter 123 6.2 Future Work 125 Reference 127 Appendix : Chip Tapeout List and Publication 133

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