儘管製程技術不斷的快速進步，奈米層級的半導體製造技術仍然無法有效解決製作導通孔(via)失敗的問題，增加冗餘導通孔(redundant via)是典型的方法可以提高晶圓良率和可靠性。在以元件單位為基礎(cell-based)的設計方式上要增加第一層冗餘導通孔插入率(redundant via1 insertion rate)，標準元件(standard cell)的設計是不可或缺的因素。本篇論文根據傳統的雙倍導通孔(double-via)以及新式的矩型導通孔(rectangle-via)，研發出一個高效率的標準元件庫(standard cell library)檢查演算法，用來找出可以增加面積的第一層金屬繞線層腳位(metal1 pins)並進行修改，此外安排腳位使用交錯的佈置方式以增加繞線空間，這樣就能有效加強第一層冗餘導通孔插入率。我們設計的標準元件庫不但很容易實施，並且適用於目前所有商業的繞線法。
為了驗證以上設計方法的效果，我們根據這些方法修改原本六五奈米製程的標準元件庫，並且跟現今先進的技術進行比較。實驗結果證實，我們設計的標準元件庫不但增加整體冗餘導通孔數達20.5％，增加第一層冗餘導通孔數達33.3％，並且減少執行時間高達44.8％。除此之外，針對傳統的雙倍導通孔方式，平均提高第一層冗餘導通孔插入率達14.8％；另外針對新式的矩型導通孔方式，我們達成100％的第一層冗餘導通孔插入率。

Despite the rapid advances in process technology, via failure is still problematic in nanometer-scale semiconductor manufacturing. Adding redundant vias is the typical approach for improving yield and reliability. Standard cells are essential for increasing the insertion rate of redundant via1s in cell-based designs. This study proposes an efficient library check and staggered pin arrangement approach that considers different configurations of redundant vias such as double-via and rectangle-via in order to increase redundant via1 insertion rate. Moreover, the proposed standard cell library is easily implemented in all currently available routers. The experimental results reveal that the proposed library improves total inserted redundant vias, total inserted redundant via1s, and total run time by 20.5%, 33.3%, and 44.8%, respectively. Compared to conventional approach, the average via1 insertion rate in double-via pattern is improved by 14.8%, and the via1 insertion rate in rectangle-via pattern is achieved at 100%.

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