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研究生： 李柏青
Po-Ching Li
論文名稱： 應用於ISM頻段之鎖相迴路晶片設計
A Phase-Locked Loop Chip Design for ISM Band Application
指導教授： 黃進芳
Jhin-Fang Huang
劉榮宜
Ron-Yi Liu
口試委員: 徐敬文
Ching-Wen Hsue
江正雄
Jen-Shiun Chiang
黃弘一
Hong-Yi Huang
學位類別： 碩士
Master
系所名稱： 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年： 2008
畢業學年度： 96
語文別： 英文
論文頁數： 113
中文關鍵詞： 鎖相迴路 、壓控震盪器
外文關鍵詞： Phase-Locked Loop, Voltage-Controlled Oscillator
相關次數： 點閱：471  下載：1 
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  •  上一筆

    • 鎖相迴路的積體電路化在無線通訊應用方面受到相當廣泛的運用，而且產品的小型化、多功能、積體化和高頻化已經是必然的趨勢。本論文的目的在於介紹頻率合成器的理論分析和實際頻率合成器的設計過程。由於常見的整數型頻率合成器有幾個取捨問題，例如頻率解析度對於迴路頻寬、相位雜訊和參考信號突波的取捨。所以本論文重於電路能改善，以期可以在製程的限制下設計出表現出色的電路。
    在本篇論文當中，我們使用了台積電0.35um 2P4M製程技術設計了兩個鎖相迴路。第一個鎖相迴路為應用於中繼式無線電系統，且涵蓋了320MHz到1100MHz的相當寬的頻寬。第二個鎖相迴路頻率涵蓋2.1GHz到3.1GHz且應用於ISM頻帶。因為相位雜訊對一個升降頻的穩定頻率來說是非常重要的，如果相位雜訊不合乎規格，容易使後級接收到的頻率被相位雜訊所干擾。相對於其他環形震盪器來說，這裡設計了一個低相位雜訊的環型震盪器，另一方面，由於未使用電感，兩個電路皆可以有效率的節省晶片面積。

    The phase lock loop in integrated was a quite widely application in communication, and the product is miniaturization, powerful function, accumulates the body and high frequency has become the inevitable tendency for fast growth wireless communication industry. The purpose of this thesis introduces the analysis frequency synthesizer and the actual design process of the frequency synthesizer. Due to the conventional integer-N frequency synthesizers suffer from fundamental tradeoffs among frequency step size, loop bandwidth, phase noise, and reference spurs. It focus on improve circuit performance, and design a better circuit in process limit.
    In this thesis, we propose two phase-locked loops in TSMC 0.35um CMOS 2P4M process technology. The first phase-locked loop is a frequency synthesizer for Trunked Radio System Applications PLL. This proposed synthesizer covers a wide frequency range from 320MHz to 1100MHz. The second phase-locked loop is also made in 0.35um process, and the frequency is from 2.1GHz to 3.1GHz for ISM band. Because of phase noise is very important to communication system, especially in offering a steady frequency of going up and down. If the phase noise does not meet to the specification, it is easy to grade of frequency reached to receive interfere by the phase noise. The ring-oscillator is designed in lower phase noise comparing with conventional ring-oscillator. On the other hand, the two circuits design reduces chip area efficiently as a result of non-inductive.

    Chapter 1 Introduction 1.1. Introduction 1.2 Focus and Contribution 1.3 Organization of this thesis Chapter 2 The Basics of PLL-Based Frequency Synthesizers 2.1 Frequency Synthesizer Architecture 2.1.1 Direct digital frequency synthesizer 2.1.2 PLL-based frequency synthesizer 2.1.3 DLL-based frequency synthesizer 2.1.4 Summary and comparison of synthesizers 2.2 Phase-Locked Loop 2.3 General Considerations 2.3.1 Time Jitter 2.3.2 Phase Noise and Spurious Tone 2.3.2 Spurious 2.4 Paper Survey Chapter 3 Analysis of Phase-Locked Loop 18 3.1 Linear Transfer Function for Integer-N PLLs 3.2 Charge Pump PLL Design 3.2.1 Second-Order PLL 3.2.2 Third-Order PLL 3.2.3 Fourth-Order PLL 3.3 Building Blocks of PLL 3.3.1 Voltage-Controlled Oscillator (VCO) 3.3.2 Frequency Divider 3.3.3 Phase Frequency Detector (PFD) 3.3.4 Charge Pump (CP) 3.4 Setting Time 3.4.1 Working Range 3.4.2 Locking time 3.4.3 Tracking and acquisition Chapter 4 A 800MHz Phase-Locked-Loop Chip Design 4.1 Introduction 4.2 Design and Simulation 4.2.1 Voltage-Controlled Oscillator 4.2.2 Frequency Divider 4.2.2.1 Multi-Modulus Divider 4.2.2.2 Divide-by-2 of TSPC Divider 4.2.3 Phase Frequency Detector 4.2.4 Charge Pump 4.2.5 System Simulation 4.3 Implement and Measurement 4.4 Summary Chapter 5 A 2.5GHz Phase-Locked-Loop Chip Design 66 5.1 Introduction 5.2 System Simulation 5.3 Design and Simulation 5.3.1 Voltage-Controlled Oscillator 5.3.2 Frequency Divider 5.3.2.1 Multi-Modulus Divider 5.3.2.1 Divide-by-2 of TSPC Divider 5.3.2.3 Source-Coupled Logic 5.3.3 Phase Frequency Detector 5.3.4 Charge Pump 5.3.5 Single-end OP Amp 5.3.6 System Simulation 5.4 Implement and measurement 5.4 Summary Chapter 6 Conclusions 6.1 Conclusions 6.2 Future Works Reference

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