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| 研究生： |
張尚揚 Shang-Yang Chang |
|---|---|
| 論文名稱： |
快閃記憶體儲存系統之開放式系統架構 An Open-System Framework for Flash-Memory Storage Systems |
| 指導教授： |
謝仁偉
Jen-Wei Hsieh |
| 口試委員: |
張立平
none 陳雅淑 none 張原豪 none |
| 學位類別： |
碩士 Master |
| 系所名稱： |
電資學院 - 資訊工程系 Department of Computer Science and Information Engineering |
| 論文出版年： | 2010 |
| 畢業學年度： | 98 |
| 語文別： | 英文 |
| 論文頁數： | 31 |
| 中文關鍵詞： | 快閃記憶體轉換層 、多階儲存單元 、記憶裝置轉換層 |
| 外文關鍵詞： | Flash Translation Layer, MLC, MTD Translation Layer |
| 相關次數： | 點閱：244 下載：9 |
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NAND flash memory has been widely adopted in consumer electronics and portable devices as a storage medium due to its light weight, shock resistance, low access latency, low power consumption, and high density natures. NAND flash memory could be classified into Single-Level Cell (SLC) and Multi-Level Cell (MLC). SLC is the earlier design of flash memory and could store 1 bit per cell. A numerous management schemes have been proposed for SLC, e.g., BAST, FAST, LAST, KAST, etc. In recent years, MLC, which stores 2 bits per cell, has gradually replaced SLC due to its lower cost and higher density. However, MLC also brings new constraints, i.e., no partial programming and sequential page writes within a block, to the management. As a result, management schemes designed for SLC could not be directly applied to MLC, or a severe performance degradation would be suffered. This paper proposes a translation layer above flash-memory medium to make it transparent to management schemes. With our translation layer, management schemes designed for SLC or MLC could be directly applied without considering the type of underlying flash memory medium. Our experiment results show that only a minor overhead would be suffered while applying our translation layer in flash-memory storage systems.
由於輕便、抗震、存取快速、低耗電以及高密度等特性，快閃記憶體廣泛地被用在消費性電子產品及手持裝置上。快閃記憶體可分成單階儲存單元和多階儲存單元兩種。前者是早期的快閃記憶體設計，每一個儲存單元可儲存一個位元的資料。現行的許多管理機制皆是為單階儲存單元所設計的，好比BAST, FAST, LAST, KAST…等。近年來，能儲存兩個位的多階儲存單元快閃記憶體，由於成本底廉，且更高的資料密度，逐漸地取代單階儲存單元為主流產品。然而，多階儲存單元快閃記憶體得承受更多的限制－部份寫入禁止以及循序分頁寫入。這兩個限制造成以往給單階儲存單元快閃記憶體的管理機制失效。此篇論文在以往的管理機制和快閃記憶體中間提出新的一層轉換機制，負責兩者間的協調。使用我們所提出的轉換層，所有舊有的管理機制可相容於各種的快閃記憶體。而在我們的實驗中，我們更可證出此高度相容性所帶來的效能影響。
[1] Y. K. A. Gupta and B. Urgaonkar. DFTL: a flash translation layer employing demand-based selective caching of page-level address mapping. In In Architectural Support for Programming Languages and Operation Systems., pages 229{240, February 2009.
[2] L.-P. Chang and T.-W. Kuo. An Adaptive Stripping Architecture for Flash Memory Storage Systems of Embedded Systems. In IEEE Eighth Real-Time and Embedded Technology and Applications Symposium (RTAS), San Jose, USA, September 2002.
[3] Y.-H. Chang, J.-W. Hsieh, and T.-W. Kuo. Improving Flash Wear-Leveling by Proactively Moving Static Data. IEEE Transactions on Computers, 59(1):53-65, January, 2010.
[4] D. S. H.Cho and Y. I. Eom. KAST: K-associative sector translation layer for NAND flash memory in real-time systems. In In Design, Automation and Test in Europe(DATE), pages 507{512, April 2009.
[5] J.-S. K. J.-U. Kang, H. Jo and J. Lee. A superblock-based °ash translation layer for CompactFlash systems. In IEEE Transactions on Consumer Electronics, pages 48(2):366-375, May 2002.
[6] J. Kim, J. M. Kim, S. H. Noh, S. L. Min, and Y. Cho. A Space-Efficient Flash Translation Layer for CompactFlash Systems. In IEEE Transactions on Consumer Electronics, Vol. 48, No. 2, pages 366{375, May 2002.
[7] S.-W. Lee, D.-J. Park, T.-S. Chung, D.-H. Lee, S. Park, and H.-J. Song. A Log Buffer-Based Flash Translation Layer Using Fully-Associative Sector Translation. In ACM Transactions on Embedded Computing Systems, Vol. 6, No. 3, Article 18, July 2007.
[8] Y.-J. K. S. Lee, D. Shin and J. Kim. LAST: locality-aware sector translation for NAND °ash memory-based storage systems. In SIGOPS Oper. Syst. Rev., page 42(6), October 2008.
[9] Testmetrix Inc. VTE2100.
