隨著無線通訊領域發展，各種晶片與其相關電路不斷湧現，為無線通訊帶來了更多的應用的可能性和發展前景，同時在製程尺度微縮下，更多電路及系統將會被更有效被整合在同一晶片。然而，科技的進步也帶來了相應的挑戰，有效整合這些不同操作時脈的子電路成了一大難題。由於電路與電路之間有不同的操作時脈，因此在運行過程中出現的時脈誤差，可能導致資料產生偏差，進而出現不正確地傳輸，這對系統的穩定性及整體性能構成了潛在威脅。在這樣情況下，鎖相迴路成為了解答，藉由同一個鎖相迴路產生的操作時脈直接或經由除頻器與其他電路進行同步，並確保子電路間能夠在彼此相對應的時間運作，從而將正確的資料進行數據。
鎖相迴路由大多由以下電路組成，相位偵測器(PD)或相位頻率偵測器(PFD)、充電汞(CP)、迴路濾波器(LF)、壓控振盪器(VCO)以及除頻器(FD)。相位偵測器或相位頻率偵測器作為第一個部件，比較出參考信號與回授信號的相位差並生成一個輸出信號，充電汞與迴路濾波器根據前一級相位頻率偵測器產生的相位差信號產生電流脈衝，經過迴路濾波器產生一個平滑的控制電壓，控制壓控振盪器產生輸出並經過除頻器回授至相位頻率偵測器，藉由各個部件不斷追蹤參考信號，最終將完成輸出穩定信號的功能。
本論文將著重於鎖相迴路兩個關鍵元件上，壓控振盪器(VCO)和注入鎖定除頻器(ILFD)。這兩個元件的性能和設計對於整個鎖相迴路的功能至關重要，因此我們將深入探討VCO及ILFD的設計原理，分享最佳實踐，並探討兩者對於鎖相迴路的功能影響。本篇論文將分為主向兩大項目，前三章節為VCO及ILFD的介紹設計並探討其工作原理，後三章節為VCO及ILFD電路模擬、量測與結論。
首先，第六章節著重於介紹一個三電感耦合變壓器互補式壓控震盪器，此架構使用TSMC 0.18 μm CMOS製程工藝設計和模擬。首先模擬VCO特性，再利用所繪製的電感佈局萃取電感s參數，後將取得的電感特性帶回VCO中進行模擬，以評估VCO的性能。在此章節我們將深入探討VCO的設計理念、原理，模擬測試以及實際的量測結果。此架構主電路由一個主電感和互補式壓控震盪器（Complementary VCO）組成振盪器，同時還使用兩個電感與主電感用來構建變壓器（Transformer）。這樣結構不僅大幅地減小了晶片的佔用面積，同時也在相位雜訊和功耗表現上有優異的性能。晶片面積為0.766×1.026 mm2。
其次，第五章節著重於使用特殊形狀的八字形電感互補式壓控震盪器，此架構使用TSMC 0.18 μm CMOS製程工藝進行設計和模擬，本章節將探討自偏壓互補式壓控震盪器的設計理念、原理，模擬測試以及實際的量測結果定。同時提出應用八字形電感的自偏壓互補式壓控震盪器，探討八字形電感對於VCO特性的影響，並且在此討論此VCO的設計理念、原理，模擬測試以及實際的量測結果定。本章節加入干擾源模擬使用八字型電感與傳統八角型電感進行模擬比較，另外本章節結合本實驗室陳暉同學電感等效模型進行驗證。整個晶片面積佔據0.716×0.641 mm2。
接續前幾章節，第六章節著重於TSMC 0.18 μm CMOS工藝下的雙頻段除二注入鎖定除頻器 (ILFD)，基於兩組LC的電容交叉耦合振盪器進行改良，分別組成低頻段(Low Band)與高頻段(High Band)的鎖定範圍。Low Band除二 ILFD 在 10.7mW 的功耗和 0 dBm 的注入信號功率下具有 4.19 GHz 至 11.8 GHz 的鎖定範圍，High Band除二 ILFD 在 8.2 mW 的功耗和 0 dBm 的注入信號功率下具有 11.3 GHz 至 12.42 GHz 的鎖定範圍，整個晶片面為0.919 ×0.745 mm2的小面積。
第七章為論文的結論，我們將回顧前幾章進行總結性的討論。藉由對論文前幾章提出的電路理論、模擬和設計的回顧，並深入探討高性能壓控振盪器和注入鎖定除頻器的應用前景，我們將討論如何將這些元件整合到射頻系統中，展示它們提高系統性能、降低功耗的潛力，以及它們對射頻領域的未來影響。

Nowadays, with the rapid development of technology in wireless communication, a variety of chips and subcircuits continue to be produced, providing numerous opportunities for innovation and application. However, this diversity also comes with a significant challenge – how to effectively integrate these subcircuits. The integration of various system sub-circuits often encounters different operating clocks, resulting in data deviations. It is in this context that phase-locked loops (PLLs) become a crucial part of the solution.
A typical PLL is mostly comprised of the following circuit components: a phase detector (PD) or a phase-frequency detector (PFD), a charge pump (CP), a loop filter (LF), a voltage-controlled oscillator (VCO), and a frequency divider (FD). The phase detector or phase-frequency detector serves as the first component, comparing the phase difference between the reference clock signal and the feedback clock signal to generate an output. The charge pump and loop filter produce current pulses based on the phase difference signal generated by the previous stage phase-frequency detector, resulting in a smooth control voltage through the loop filter. This control voltage regulates the output signal generated by the voltage-controlled oscillator, which is then fed back to the phase-frequency detector through the frequency divider.
This thesis focuses on two important components: one is a Voltage-Controlled Oscillator (VCO) and the other one is an Injection-Locked Frequency Divider (ILFD). The performance and design of these two components are of paramount importance to the overall functionality of the PLL. We will delve into their design principles and share best practices to ensure their effective contribution to the PLL's operation, achieving highly accurate clock synchronization and enhancing the system's performance.
The first part introduces an LC-tank Voltage-Controlled Oscillator (VCO) with a trifilar transformer fabricated using the TSMC 0.18 μm CMOS process. This section includes the circuit design, operational principles, and measurement results of the LCVCO. We first simulate the inductor characteristics using Advanced Design System (ADS) and then simulate the VCO characteristics using Cadence. This architecture comprises an inductor, a complementary voltage-controlled oscillator, and two additional inductors forming a transformer. This transformer configuration significantly reduces the area of the chip while improving phase noise performance and reducing power consumption. The entire chip occupies a compact area of 0.766×1.026 mm².
Furthermore, chapter 5 presents a self-biased complementary Voltage-Controlled Oscillator (VCO) with an 8-shaped inductor fabricated using the TSMC 0.18 μm CMOS process. This part includes the circuit design, operational principles, and a comparison of simulated results with measured results. The 8-shaped inductor is compared to the octangle inductor, and the former has better interference suppression capabilities than the latter. The whole chip occupies an area of 0.716×0.641 mm².
Chapter 6 presents a Dual resonator Injection-Locked Frequency Divider (ILFD) fabricated using TSMC 0.18 μm CMOS process. This structure contains two divided-by-two ILFDs, and the two ILFDs constitute the locking ranges for the Low Band resonator and High Band resonator. The Low Band ILFD achieves a locking range from 4.19 GHz to 11.8 GHz with 10.7 mW. The High Band ILFD achieves a locking range from 11.3 GHz to 12.42 GHz with 8.2 mW power consumption And the whole chip occupies an area of 0.919 ×0.745 mm².
Chapter 7 presents as the conclusion of the entire thesis, where we will review and conduct a comprehensive discussion of the preceding chapters. By revisiting the circuit theories, simulations, and designs proposed in the earlier chapters, and delving into the potential applications of high-performance VCO and ILFD, we will explore how to seamlessly integrate these components into RF systems. This will showcase their potential to enhance system performance, reduce power consumption, and enable new functionalities, as well as their impact on the future of the RF field.

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