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研究生: 林翰毅
Han-Yi Lin
論文名稱: HLC: Software-based Half-Level Cell Flash Memory
HLC: Software-based Half-Level Cell Flash Memory
指導教授: 謝仁偉
Jen-Wei Hsieh
口試委員: 楊佳玲
Chia-Lin Yang
張立平
Li-Pin Chang
吳晉賢
Chin-Hsien Wu
學位類別: 碩士
Master
系所名稱: 電資學院 - 資訊工程系
Department of Computer Science and Information Engineering
論文出版年: 2014
畢業學年度: 102
語文別: 英文
論文頁數: 44
中文關鍵詞: NAND flash memorysolid-state drives (SSDs)reliabilityendurance
外文關鍵詞: NAND flash memory, solid-state drives (SSDs), reliability, endurance
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In recent years, flash memory has been widely used in embedded systems, portable devices, and high-performance storage products due to its non-volatility, shock resistance, low power consumption, and high performance natures. To reduce the product cost, multi-level-cell flash memory (MLC) has been proposed; compared with the traditional single-level-cell flash memory (SLC) that only stores one bit of data per cell, each MLC cell can store two or more bits of data. Thus MLC can achieve a larger capacity and reduce the cost per unit. However, MLC also suffers from the degradation in both performance and reliability. In this paper, we try to enhance the reliability and reduce the product cost of flash-memory based storage devices from a totally different perspective. We propose a half-level-cell (HLC) management scheme to manage and reuse the worn-out space in SSD; through our management scheme, the system can treat two corrupted pages as a normal page without sacrificing performance and reliability. To the best of our knowledge, this is the first research that reclaims free space by reviving the corrupted pages. The experiment results show that the lifetime of SSD can be extended by 48.54%, and the response time of SSD cache can be improved by 17.99% for the trace of general users applications with our proposed HLC management scheme.


In recent years, flash memory has been widely used in embedded systems, portable devices, and high-performance storage products due to its non-volatility, shock resistance, low power consumption, and high performance natures. To reduce the product cost, multi-level-cell flash memory (MLC) has been proposed; compared with the traditional single-level-cell flash memory (SLC) that only stores one bit of data per cell, each MLC cell can store two or more bits of data. Thus MLC can achieve a larger capacity and reduce the cost per unit. However, MLC also suffers from the degradation in both performance and reliability. In this paper, we try to enhance the reliability and reduce the product cost of flash-memory based storage devices from a totally different perspective. We propose a half-level-cell (HLC) management scheme to manage and reuse the worn-out space in SSD; through our management scheme, the system can treat two corrupted pages as a normal page without sacrificing performance and reliability. To the best of our knowledge, this is the first research that reclaims free space by reviving the corrupted pages. The experiment results show that the lifetime of SSD can be extended by 48.54%, and the response time of SSD cache can be improved by 17.99% for the trace of general users applications with our proposed HLC management scheme.

1 Introduction 2 Background and Related Work 3 Design of HLC Management Layer 3.1 Overview of HLC 3.2 HLC Data Structure 3.3 Write Flow 3.4 Read Flow 3.5 ECC Extension 4 Implementation Remark 4.1 Multilevel Parallelism 4.2 Garbage Collection 5 Experiments 5.1 Experimental Setup 5.2 Experimental Results 5.2.1 Lifetime Experiment 5.2.2 Response Time 5.2.3 Cache Hit Ratio of Read Request 6 Conclusion

[1] F. Chen, T. Luo, and X. Zhang, “CAFTL: A Content-Aware Flash Translation Layer Enhancing the Lifespan of Flash Memory based Solid State Drives,” in FAST, 2011, pp. 77–90.
[2] Y. Park and J.-S. Kim, “zFTL: power-efficient data compression support for nand flash-based consumer electronics devices,” IEEE Trans. Consumer Electronics, vol. 57, no. 3, pp. 1148–1156, 2011.
[3] S. Lee, T. Kim, J. Park, and J. Kim, “An integrated approach for managing the lifetime of flash-based ssds,” in DATE, 2013, pp. 1522–1525.
[4] M.-C. Yang, Y.-H. Chang, C.-W. Tsao, and P.-C. Huang, “New ERA: new efficient reliability-aware wear leveling for endurance enhancement of flash storage devices,” in DAC, 2013, p. 163.
[5] X. Jimenez, D. Novo, and P. Ienne, “Phoenix: reviving MLC blocks as SLC to extend NAND flash devices lifetime,” in DATE, 2013, pp. 226–229.
[6] Y.-J. Woo and J.-S. Kim, “Diversifying wear index for MLC NAND flash memory to extend the lifetime of SSDs,” in EMSOFT, 2013, pp. 1–10.
[7] C. Wang and W.-F. Wong, “Extending the lifetime of NAND flash memory by salvaging bad blocks,” in DATE, 2012, pp. 260–263.
[8] J.-W. Hsieh, Y.-H. Chang, and Y.-S. Chu, “Implementation strategy for downgraded flash-memory storage devices,” ACM Trans. Embedded Comput. Syst., vol. 12, no. 1s, p. 60, 2013.
[9] R.-S. Liu, C.-L. Yang, C.-H. Li, and G.-Y. Chen, “Duracache: a durable ssd cache using mlc nand flash,” in DAC, 2013, p. 166.
[10] K. Lee and A. Orailoglu, “High durability in NAND flash memory through effective page reuse mechanisms,” in CODES+ISSS, 2010, pp. 205–212.
[11] Micron, “NAND Flash Memory MT29F4G08AAA, MT29F8G08BAA, MT29F8G08DAA, MT29F16G08FAA,” Micron, Tech. Rep., 2006.
[12] Micron, “TN-29-25: Improving Performance Using Two-Plane Commands Introduction,” Micron, Tech. Rep., 2007.
[13] Samsung, “K9GAG08B0M (2G x 8 Bit NAND Flash Memory) Datasheet,” Samsung, Tech. Rep., 2006.
[14] Samsung, “NAND Flash Memory K9GAG08B0M, K9GAG08U0M, K9LBG08U1M,” Samsung, Tech. Rep., 2007.
[15] J.-W. Hsieh, H.-Y. Lin, and D.-L. Yang, “Multi-channel architecture-based ftl for reliable and high-performance ssd,” IEEE Transactions on Computers, vol. 99, no. PrePrints, p. 1, 2013.
[16] R. Micheloni, L. Crippa, and A. Marelli, Inside NAND Flash Memories. Springer Science+Business Media, 2010.
[17] Sandisk, “Solid State Drives Data Reliability and Lifetime White Paper ,” Sandisk, Tech. Rep., 2008.
[18] Y. Cai, E. F. Haratsch, and K. Mai, “Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis,” in IEEE DATE, 2012.
[19] L.-P. Chang, “A hybrid approach to nand-flash-based solid-state disks,” IEEE Trans. Computers, vol. 59, no. 10, pp. 1337–1349, 2010.
[20] L.-P. Chang and C.-D. Du, “Design and implementation of an efficient wear-leveling algorithm for solid-state-disk microcontrollers,” ACM Trans. Design Autom. Electr. Syst., vol. 15, no. 1, 2009.
[21] Umasstracerepository. [Online]. Available: http://traces.cs.umass.edu/index.php/Storage/Storage
[22] Intel, “Intel MD516 NAND Flash Memory JS29F16G08AAMC1, JS29F32G08CAMC1, JS29F64G08FAMC1,” Intel, Tech. Rep., 2007.

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