研究生: |
顏子祥 Zih-Siang Yan |
---|---|
論文名稱: |
降低換層差動傳輸線之共模與差模雜訊 Reduction of Common-Mode and Differential-Mode Noise for Multilayers Differential Transmission Line |
指導教授: |
王蒼容
Chun-Long Wang |
口試委員: |
楊成發
Chang-Fa Yang 周詠晃 Young-Huang Chou |
學位類別: |
碩士 Master |
系所名稱: |
電資學院 - 電子工程系 Department of Electronic and Computer Engineering |
論文出版年: | 2016 |
畢業學年度: | 104 |
語文別: | 中文 |
論文頁數: | 152 |
中文關鍵詞: | 差動傳輸線 、多層板 、差模雜訊 、共模雜訊 |
外文關鍵詞: | differential transmission line, multilayers, differential mode noise, common mode noise |
相關次數: | 點閱:361 下載:9 |
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本論文提出非對稱via補償的強耦合差動傳輸線,可以有效地降低轉角差動傳輸線所產生的共模雜訊以及差模反射。適當地設計非對稱via來補償強耦合差動傳輸線的內外路徑差,可以有效地降低輸出端的共模雜訊,同時,適當地設計非對稱via達成阻抗匹配,可以降低輸入端的差模反射。在頻域方面,7 GHz以前差模轉共模的模轉換皆在-20 dB以下;在時域方面,TDT共模雜訊從0.038 V減少至0.016 V。
為了簡化設計,我們提出寬邊平行耦合傳輸線的架構,這個架構為平衡的架構,因此輸出端的模轉換本身就很低,只要適當地設計阻抗匹配,就可以使輸入端的差模反射達到很低的位準。在頻域方面,差模轉共模穿透量與差模轉共模反射量皆在-30 dB以下,而差模到差模反射量在-20 dB 以下;在時域的方面,TDR差模雜訊從0.06 V降低至0.024 V,TDR共模雜訊從0.015 V降低至0.005 V,TDT共模雜訊為0.001 V。
In this thesis, a tightly-coupled multi-layer differential transmission line using the unsymmetrical differential vias is proposed. The proposed structure could effectively reduce the differential-to-common mode conversion and differential-to-differential mode reflection. By adequately designing the unsymmetrical differential vias to compensate the path difference between the inner and outer paths of the differential transmission line, the common-mode noise at the output port could be greatly reduced. Meanwhile, by adequately designing the unsymmetrical differential vias to match the system impedance, the differential-mode reflection at the input port could be greatly reduced. As can be seen from the frequency-domain results, the differential-to-common mode conversion is less than -20 dB from DC to 7 GHz. As can be seen from the time-domain results, the TDT common-mode noise is reduced from 0.038 V to 0.016 V.
In order to simplify the design procedures, a multi-layer differential transmission line using the broadside-coupled line is proposed. Since the proposed structure is a balanced structure, the differential-to-common mode conversion at the output port would eventually be very low. By adequately designing the broadside-coupled line to match the system impedance, the differential-to-differential mode reflection at the input port could be greatly reduced. As can be seen from the frequency-domain results, the differential-to-common conversion and reflection are all less than -30 dB while the differential-to-differential mode reflection is less than -20 dB. As can be seen from the time-domain results, the TDR differential-mode noise is reduced from 0.06 V to 0.024 V; the TDR common-mode noise is reduced from 0.015 V to 0.005 V; the TDT common-mode noise is reduced to 0.001 V.
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