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研究生： 陳俊吉
Chun-Chi Chen
論文名稱： 互補式金氧半時域智慧型溫度感測器之設計與實作
Design and Realization of CMOS Time Domain Smart Temperature Sensors
指導教授： 陳伯奇
Poki Chen
口試委員: 吳靜雄
Jingshown Wu
劉深淵
Shen-Iuan Liu
學位類別： 博士
Doctor
系所名稱： 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年： 2007
畢業學年度： 95
語文別： 英文
論文頁數： 148
中文關鍵詞： 智慧型溫度感測器 、時間至數位轉換器 、數位至時間轉換器
外文關鍵詞： Smart temperature sensor, time-to-digital converter (TDC), digital-to-time converter (DTC)
相關次數： 點閱：321  下載：4 
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    • 20世紀末期以來，為了連結個人電腦或微控制器，類比至數位轉換器或數位至類比轉換器被廣泛地與溫度感測器相結合而將其稱為智慧型溫度感測器。然而，此種智慧型電路需要精巧的校正電路以達成足夠之精確度，結果晶片面積變的更大或是電路更形複雜，如此將使得智慧型溫度感測器不適用於可攜式系統甚至於難以整合於系統晶片或是超大型積體電路。
    以可輕易地實現內建晶片積體化與可重複矽智財為目標，本論文發表了三種互補式金氧半之時域智慧型溫度感測器與一種時域溫度警示調節器。為了符合可攜式系統之低成本及低功耗需求，我們提出了由反相器延遲線組成之新式溫度感測技術，以時域取代傳統之電壓域來實現精簡之電路架構，無需額外之校正電路與雷射修整程序亦可獲得高精確度；本論文亦提出溫度補償電路作為時序參考源，其功能與電壓域之能係參考源相仿。相對應地，時間至數位轉換器或數位至時間轉換器成功地取代類比至數位轉換器及數位至類比轉換器以作數位輸出或溫度設定功能。
    這4顆嶄新的智慧型溫度感測器皆以台積電互補式金氧半0.35-µm數位標準製程來製作，且經實測驗證成功。第一個具正溫度係數之智慧型溫度感測器的晶片面積只有0.175 mm2，經兩點校正後所達成之量測誤差為-0.7~+0.9°C，其有效溫度解析度優於0.16°C且功率消耗低於10µW。而負溫度係數之版本則改採兩相鄰延遲元件共享一溫度補償電路以進一步減少晶片面積與功率消耗，此第二代溫度感測器僅佔用0.09 mm2，是目前所有CMOS智慧型溫度感測器中面積最小者，其有效解析度與量測誤差進步至0.09°C, ±0.6°C，功率消耗則下降至1.5 µW。爾後，一個具可程式設定之新穎8位元溫度警示調節器被提出，藉由一簡單之多工器來達成溫度設定之功能，此晶片面積為0.4 mm2，且誤差小於±0.8°C，其解析度為0.5°C，而功率消耗則為9 µW。最後，本論文提出以循序逼近式暫存器 (SAR)為基礎之智慧型溫度感測器，乃是由上述溫度警示調節器衍生而來，搭配SAR 控制邏輯以執行待測溫度之數位轉換；此晶片具10輸出位元，面積為0.6 mm2，其解析度則為0.09°C，在本論文所提出之電路中擁有最佳之±0.3°C量測誤差。
    論文所提及之智慧型溫度感測器，將可使智慧型溫度感測器於低成本與低功率應用中提供更加的可行性與可靠度。與此同時，就互補式金氧半反相器延遲線、時間至數位與數位至時間轉換器而言，本研究亦開創出有關溫度方面的應用

    In the late 20th century, ADCs (analog-to-digital converters) or DACs (digital-to-analog converters) were integrated into thermal sensors to compose so-called integrated smart temperature sensors for the easy interfacing with computers or microcontrollers. To achieve a sufficient accuracy, many elaborate on-chip calibrated techniques were required in the smart circuits. However, to achieve this, either the chip area would become larger or the circuits more complicated, making the smart temperature sensors less applicable to low-cost portable applications and even less suitable for SOC or VLSI integration.
    To ease on-chip integration and SIP (silicon intellectual property) reuse, three CMOS time domain smart temperature sensors and one CMOS time domain thermostat are presented in this dissertation. To achieve low-cost and low-power in portable systems, a novel temperature sensing technique, composed of a NOT gates delay line in time domain instead of the conventional voltage domain is proposed to realize a simple architecture without the need for additional on-chip calibrated techniques and laser trimming processes. A thermal-compensation circuit is proposed as the timing reference whose function is similar to that of bandgap reference in the voltage domain. Accordingly, a TDC (time-to-digital converter) or a DTC (digital-to-time converter) is successfully utilized instead of ADC or DAC to perform digital output coding or temperature set-point programming.
    Four proposed smart temperature sensors were fabricated in the TSMC CMOS 0.35-µm 2P4M digital process and successfully verified by experiments. The first work with positive temperature coefficient owns a small area of 0.175 mm2 and achieves a measurement error less than -0.7°C ~+0.9°C after two point calibration. The effective resolution is better than 0.16°C, and the power consumption is under 10 µW. To further reduce the chip size and the power consumption, each thermal-compensation circuit is shared by two adjacent delay cells in the negative coefficient version to achieve the smallest chip area of 0.09 mm2 among all smart temperature sensors ever proposed. The resolution and measurement errors are reduced to 0.09°C, ±0.6°C, respectively. The power consumption is merely 1.5µW. Moreover, a novel 8-bit thermostat with programmable set-point was proposed. A simple multiplexer is utilized to program the temperature set-point. The chip area is 0.4mm2, and the achieved measurement error is under ±0.8°C with 0.5°C effective resolution and 9 µW power consumption. Finally, a successive-approximation-register (SAR)-based smart temperature sensor with binary-weighted search algorithm is developed based on the proposed thermostat. A SAR control logic is adopted for digital output coding control. The chip area of the 10-bit smart sensor is 0.6 mm2, and the effective resolution is 0.09°C. The chip has the smallest measurement error of±0.3°C among all proposed circuits in this dissertation.
    These proposed sensors allow more flexibility and reliable performance for utilizing smart temperature sensors in portable applications. In addition, as far as CMOS NOT gates delay lines, TDCs and DTCs are concerned, a brand new application in temperature measurement is developed.

    TABLE OF CONTENTS CHINESE ABSTRACT I ENGLISH ABSTRACT III ACKNOWLEDGEMENT V TABLE OF CONTENTS VII LIST OF FIGURES X LIST OF TABLES XIII CHAPTER 1 INTRODUCTION 1 1.4 BACKGROUND 1 1.2 THERMAL MANAGEMENT IN COMPUTER SYSTEMS 3 1.3 A TYRE MONITORING SYSTEM 4 1.4 WHY CMOS TECHNOLOGY 6 1.5 CMOS INTEGRATED SMART TEMPERATURE SENSORS 7 1.6 MOTIVATION AND OBJECTIVES 8 1.7 DISSERTATION ORGANIZATION 9 CHAPTER 2 REVIEW 11 2.1 INTRODUCTION TO TEMPERATURE SENSORS 11 2.1.1 Conventional Temperature Sensing 11 2.1.2 Semiconductor (Integrated) Temperature Sensors 12 2.2 SEMICONDUCTOR TEMPERATURE SENSORS AND BANDGAP REFERENCES 14 2.2.1 VBE Temperature Sensor and PTAT Temperature Sensor 16 2.2.2 Bandgap Reference 18 2.2.3 Non-idealities in CMOS Bandgap References and VBE 20 2.2.4 Offset and Noise in CMOS Amplifiers 23 2.2.5 Dynamic Offset-Cancellation Techniques and Triming 24 2.3 OTHER TEMPERATURE SENSING TECHNIQUES 26 2.3.1 Temperature to Frequency Conversion 27 2.3.2 Temperature to Duty-Cycle Conversation 28 2.3.3 Temperature Sensor with Logic Output 29 2.4 DIGITAL CODE CONVERSION 30 2-4.1 Sigma-Delta A-to-D Conversation 31 2-4.2 Clock-Synchronized Sensor 32 2.5 IMPORTANT SPECIFICATIONS OF THE CMOS SMART TEMPERATURE SENSOR 33 2.5.1 Resolution and Accuracy 33 2.5.2 Power Consumption 34 2.5.3 Cost 35 2.6 SUMMARY 36 CHAPTER 3 DESIGN AND REALIZATION OF TIME DOMAIN SMART TEMPERATURE SENSORS 37 3.1 INTRODUCTION 38 3.2 TIME DOMAIN TEMPERATURE SENSOR AND TIMING REFERENCE 43 3.2.1 Proposed Temperature-to-Pulse Generator 44 3.2.2 Temperature Characteristic of TDDL 45 3.2.3 Thermal-Compensation Circuit for TRDL 47 3.3 TIME-TO-DIGITAL CONVERSION 50 2.3.1 Introduction to CMOS Time-to-Digital Converter 51 2.3.2 Cyclic CMOS Time-to-Digital Converter 54 3.4 SMART TEMPERATURE SENSOR WITH POSITIVE TEMPERATURE COEFFICIENT 58 2.4.1 Temperature-to-Pulse Generator with Positive Temperature Coefficient 58 2.4.2 Experiment Results 58 3.5 SMART TEMPERATURE SENSOR WITH NEGATIVE TEMPERATURE COEFFICIEN 63 3.5.1 Temperature-to-Pulse Generator with Negative Temperature Coefficient 64 3.5.2 Experiment Results 65 3.6 SUMMARY 69 CHAPTER 4 DESIGN AND REALIZATION OF A MIXED-MODE TEMPERATURE SENSOR WITH SET-POINT PROGRAMMING 71 4.1 INTRODUCTION 71 4.2 MAIN BUILDING BLOCKS 75 4.2.1 Delay Lines 77 4.2.2 Digital-to-Time Conversion 78 4.2.3 Delay Generation in the TRDL with a Multiplexer 79 4.2.4 Multiplexer and Timing Comparator 82 4.3 EXPERIMENT RESULTS 85 4.4 SUMMARY 89 CHAPTER 5 DESIGN AND IMPLEMENTATION OF A SAR-BASED SMART TEMPERATURE SENSOR 91 5.1 INTRODUCTION 91 5.2 A SAR-BASED SMART TEMPERATURE SENSOR 93 5.2.1 Time Offset Cancellation Circuit 94 5.2.2 DDLL and Proposed SARTRDL 95 5.2.3 Proposed TRDL with Binary Searching Algorithm 99 5.2.4 A TDDL 103 5.2.5 Timing Comparator 104 5.2.6 SAR Control Logic 105 5.3 EXPERIMENT RESULTS 109 5.4 SUMMARY 112 CHAPTER 6 CONCLUSION 115 REFERENCES 119 PUBLICATION LIST 129 LIST OF FIGURES Fig. 1-1. Thermal management in computer systems. 3 Fig. 1-2. Operation principle of the tyre monitoring system. 5 Fig. 1-3. Communication between a temperature sensor and a computer/controller though an ADC. 7 Fig. 2-1. Cross section of a vertical pnp transistor in an n-well CMOS process. 14 Fig. 2-2. Base-emitter voltages VBE1 and VBE2 of two identical transistors with different emitter areas but biased at the same current versus temperature.. 16 Fig. 2-3. Simple VPTAT generator. 17 Fig. 2-4. Conceptual block diagram of the bandgap reference circuit. 19 Fig. 2-5. Typical schematic of bandgap reference as well as its behavior versus temperature. 19 Fig. 2-6. Schematic of a traditional CMOS bandgap reference with non-idealities. 20 Fig. 2-7. Plot of the voltage VBE versus temperature. 22 Fig. 2-8. Noise power spectrum of CMOS OPAMP.. 24 Fig. 2-9. Deviation of VREF caused by deviation in the base-emitter voltage VBE and PTAT voltage mVBE. 25 Fig. 2-10. (a) Adjusted emitter area (b) adjusted resistor 26 Fig. 2-11. Simplified example of the temperature-to-frequency converter. 27 Fig. 2-12. Simplified example of the duty-cycle converter. 28 Fig. 2-13. Simplified example of the temperature sensor with logic output. 29 Fig. 2-14. Block diagram of the digital temperature sensor with ADC. 30 Fig. 2-15. Block diagram of the sigma-delta conversion. 31 Fig. 2-16. Block diagram of the clock-synchronized sensor. 32 Fig. 3-1. Architecture of conventional smart temperature sensor.. 40 Fig. 3-2. Block diagram of the proposed smart temperature sensor. 43 Fig. 3-3. Architecture of time domain smart temperature sensor. 44 Fig. 3-4. Circuit of time domain smart temperature sensor. 44 Fig. 3-5. Circuirt of the simple temperature-to-pulse generator. 45 Fig. 3-6. Circuit of the proposed temperature-to-pulse generator. 47 Fig. 3-7. Width offset reduction accomplished by TRDL. 48 Fig. 3-8. Delay cell used in TRDL. 48 Fig. 3-9. Simulation result of the temperature-to-pulse generator. 50 Fig. 3-10. Block diagram and timing diagram of the counter-based TDC with interpolators. 52 Fig. 3-11. Block diagram of the cyclic TDC. 55 Fig. 3-12. Effect of the gates’ inhomogeneity on pulse width. 56 Fig. 3-13. Microphotograph of the realized chip. 58 Fig. 3-14. Measurement setup of the test chip. 59 Fig. 3-15. The measurement results of 25 test chips. 60 Fig. 3-16. Process variation of the effective resolution for 25 test chips. 61 Fig. 3-17. The measurement errors of 25 test chips. 61 Fig. 3-18. Supply voltage sensitivity of the proposed circuit. 62 Fig. 3-19. Generated time interval with negative thermal coefficient. 64 Fig. 3-20. Modified delay cell used in TRDL. 65 Fig. 3-21. Microphotograph of the realized chip. 65 Fig. 3-22. Measurement results of 16 test chips. 67 Fig. 3-23. Measurement errors of 16 test chips. 67 Fig. 3-24. Process variation of the effective resolution for 16 test chips. 68 Fig. 3-25. Supply voltage sensitivity of the proposed circuit. 68 Fig. 4-1. Conventional temperature sensor with programmable set point.. 74 Fig. 4-2. Operation principle of conventional temperature sensor. 75 Fig. 4-3. Proposed time-domain temperature sensor with programmable set point… 76 Fig. 4-4. Operation principle of the proposed temperature sensor. 76 Fig. 4-5. Circuits for delay lines. 78 Fig. 4-6. Timing diagram of operation principle between two delay lines. 78 Fig. 4-7(a). Combination of delay adjustment MUX and TRDL. 80 Fig. 4-7(b). Timing diagram of the fig. 4-7(a). 80 Fig. 4-8. Operation principle of the proposed temperature sensor with TRDL. 81 Fig. 4-9. Binary phase detector and its phase response. 82 Fig. 4-10. Structure of the MUX and timing comparator in the proposed circuit. 83 Fig. 4-11. Timing diagram of timing comparator. 84 Fig. 4-12. Schematic and truth table of adopted timing comparator. 84 Fig. 4-13. Microphotograph of the proposed circuit. 85 Fig. 4-14. Measurement setup of the test chip. 85 Fig. 4-15. Trip temperature versus programmed set point. 87 Fig. 4-16. Measurement error under 2nd order curvature correction. 87 Fig. 4-17. Effective resolutions of 6 test chips. 88 Fig. 4-18. Effective resolution under supply voltage variation.. 88 Fig. 5-1. Conceptual architecture of the smart temperature sensor.. 92 Fig. 5-2. Implemented architecture of the proposed smart temperature sensor.. 93 Fig. 5-3. Schematic of the time offset cancellation circuit.. 94 Fig. 5-4. Simplified block diagram of the proposed sensor with TRDL, timing comparator and control logic. 95 Fig. 5-5. Typical block diagram of DDLL. 96 Fig. 5-6. Block diagram of register-controlled scheme. 96 Fig. 5-7. Block diagram of counter-controlled scheme. 97 Fig. 5-8. Block diagram of SAR-controlled DDL. 98 Fig. 5-9. Examplified timing diagram for 4-bit SAR in (a) voltage domain and (b) time domain. 98 Fig. 5-10. Architecture of binary-weighted delay line. 99 Fig. 5-11. Adopted TRDL with binary-weighted structure. 100 Fig. 5-12. Timing diagram of 3-bit digital-controlled delay line. 101 Fig. 5-13. Schematic of the k-th segment. 102 Fig. 5-14. Simplified block diagram of a 3-segment, 6-bit delay line. 103 Fig. 5-15. Block of diagram of the TDDL. 103 Fig. 5-16. Timing diagram of operation principle between two delay lines. 104 Fig. 5-17. Main block diagram of the control logic. 105 Fig. 5-18. Schematic of the initialization circuit. 105 Fig. 5-19. Schematic of the 10-bit SAR circuit. 106 Fig. 5-20. Internal structure of the kth FF and corresponding truth table. 107 Fig. 5-21(a).Schematic of decoder. 108 Fig. 5-21(b).Schematic of multiplexer. 108 Fig. 5-22. Microphotograph of the SAR_based sensor. 109 Fig. 5-23. Measurement setup of the test chip.. 110 Fig. 5-24. Measurement results with 8 test chips. 110 Fig. 5-25. Measurement errors with 8 test chips. 110 Fig. 5-26. Effective resolution with 8 test chips. 111 Fig. 5-27. Effective resolution with voltage variation. 112 LIST OF TABLES Table 2-1. Comparison of Temperature Sensors. 14 Table 2-2. Error in CMOS bandgap references.. 22 Table 3-1. Common specifications for smart temperature sensors 40 Table 3-2. Performance of proposed smart temperature sensor with positive thermal coefficient 63 Table 3-3. Performance of proposed smart temperature sensors with negative thermal coefficient 68 Table 4-1. Measured Performance of the proposed thermostat 90 Table 5-1. Measured performance of the SAR-based sensor 113 Table 6-1. Performances comparison of recent smart temperature sensors 118

    References

    [1] H. Chiueh, J. Drape, and J. Choma, “A Dynamic Thermal Management Circuit for System-On-Chip Designs,” Analog Integrated Circuits and Signal Processing, vol. 36, pp. 175–181, 2003.
    [2] M. Smith, “Measurement temperatures on computer chips with speed and accuracy-a new approach using silicon sensors and off chip processing,” Analog Dialogue, vol. 33, no. 4, pp. 1-5, Apr. 1999.
    [3] A. Bakker and J. H. Huijsing, “High accuracy CMOS smart temperature sensors,” Kluwer Academic Publishers, 2000.
    [4] B. Razavi, “Design of analog CMOS integrated circuits,” McGRAW-HILL publishers, 2000.
    [5] M. Tuthill, “A Switched-Current, Switched-Capacitor Temperature-Sensor in 0.6-µm CMOS”, IEEE J. Solid-State Circuits, vol. 33, pp. 1117-1122, July 1998.
    [6] Y. P. Tsividis and R. W. Ulmer, “A CMOS voltage reference,” IEEE J. Solid-State Circuits, vol. 13, pp. 774-778, Dec. 1978.
    [7] P. Krummenacher and H. Oguey, “Smart Temperature Sensor in CMOS Technology,” Sensors and Actuators, vol. A21, pp. 636-638, 1990.
    [8] Databeans, “2006 Temperature Sensors,” http://www.databeans.com
    [9] G. Wang and G. C. M. Meijer “The temperature characteristics of bipolar transistors for CMOS temperature sensor,” in Proc. Eurosensors, Sept. 1999, pp. 553-556.
    [10] G. C. M. Meijer, G. Wang, and F. Fruett, “Temperature sensors and voltage references implemented in CMOS technology,” IEEE Sensors Journal, vol. 1, pp. 225-234, 2001.
    [11] G. C. M. Meijer, “Thermal Sensors based on Transistors,” Sensors and Actuators, vol. 10, pp. 103-125, 1986.
    [12] R. J. Widlar, “New developments in IC voltage regulators,” IEEE J. Solid-State Circuit, vol. 6, pp. 2-7, Feb. 1971.
    [13] K. E. Kuijk, “A precision reference voltage source,” IEEE J. Solid-State Circuit, vol. 8, pp. 226-236, Jun. 1973.
    [14] B. S. Song and P. R. Gray, “A precision curvature compensated CMOS bandgap reference,” IEEE J. Solid-State Circuits, vol. 18, no. 12, pp. 634-643, Dec. 1983.
    [15] M. Gunawan, G. C. M. Meijer, J. Fonderie and J. H. Huijsing, “A curvature corrected low voltage bandgap reference,” IEEE J. Solid-State Circuits, vol. 28, no. 6, pp. 667-670, June 1993.
    [16] A. Bakker, K. Thiele, and J. H. Huijsing, “A CMOS Nested-Chopper Instrumentation Amplifier with 100-nV Offset,” IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1877-1883, Dec. 2000.
    [17] C.-G. Yu and R. L. Geiger, “An automatic offset compensation scheme with ping-pong control for CMOS operational amplifiers,” IEEE J. Solid-State Circuits, vol. 29, no. 5, pp. 601-610, May. 1994.
    [18] C. C. Enz and G. C. Temes, “Circuit techniques for reducing the effect of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization,” IEEE J. Solid-State Circuits, vol. 31, pp. 1584-1614, Nov. 1996.
    [19] C. B. Wang, “A 20 bit 25kHz delta sigma A/D converter utilizing frequency-shaped chopper stabilization scheme,” in Proc. IEEE CICC, 2000, pp. 9-12.
    [20] A. Bakker, K. Thiele, and J. H. Huijsing, “A CMOS chopper opamp with integrated low-pass filter,” in Proc. IEEE ESSCIRC, Sept. 1997, pp. 200-203.
    [21] S. Y. Yurish, “Data Acquisition Systems for Quasi-Digital Temperature Sensors Based on Universal Frequency-to-Digital Converter,” Sensors and Actuators, vol. 57, pp. 341-351, Jul. 2005.
    [22] N. V. Kirianaki, S. Y. Yurish, N. O. Shpak, and V. P. Deynega, “Data Acquisition and Signal Processing for Smart Sensors,” John Wiley & Sons, 2002.
    [23] V. Szekely, C. Marta, Z. Kohari, and M. Rencz, “CMOS sensors for on-line thermal monitoring of VLSI circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 5, no. 3, pp. 270-276, Sept. 1997.
    [24] V. Szckely, M. Rencz, A. Pahi, and B. Courtois, “Thermal monitoring and testing of electronic systems”, IEEE Trans. components and packaging technology, vol. 22, no. 2, pp. 231-237, Jun. 1999.
    [25] K. Ueno, T. Hirose, T. Asai and Y. Amemiya, “Ultralow-Power Smart Temperature Sensor with Subthreshold CMOS Circuits,” in Proc. IEEE ISCAPS, 2006, pp. 546-549.
    [26] G. C. M. Meijer, R. van Gelder, V. Nooder, J. van Drecht and H. Kerkvliet, “A Three-Terminal Integrated Temperature Transducer with Microcomputer Interfacing,” Sensors and Actuators, A-18, pp. 195-260, 1989.
    [27] Z. Jianping, L. Yu, X. Haiqing, and W. Jian, “CMOS Digital Integrated Temperature Sensor” in Proc. IEEE ASICON, 2005, pp. 310-313.
    [28] Microchip Inc. “TC620 series Logic Output Temperature Sensor” http://www.microchip.com
    [29] F. R. Riedijk and J. H. Huijsing, “An Integrated Absolute Temperature Sensor with Sigma-Delta A-D Conversion,” Sensors and Actuators, A-34, pp. 249-256, 1992.
    [30] A. Bakker and J. H. Huijsing, “Micropower CMOS temperature sensor with digital output,” IEEE J. Solid-State Circuits, vol. 31, pp. 933-937, July 1996.
    [31] D. Marsh, “Silicon sensors harness thermal management,” EDN, pp. 43-55, Dec. 2003.
    [32] A. Bakker and J. H. Huijsing, “A Low-Cost High-Accuracy CMOS Smart Temperature Sensor,” in Proc. IEEE ESSCIRC, Sept. 1999, pp. 302-305.
    [33] M. A. P. Pertijs, A. Niederkorn, M. Xu, B. McKillop, A. Bakker, and J. H. Huijsing, “A CMOS Smart Temperature Sensor with a 3σ Inaccuracy of ±0.1C from –55oC to 125oC,” IEEE J. Solid-State Circuits, vol. 40, pp. 2805-2815, Dec. 2005.
    [34] A. Bakker and J. H. Huijsing, “CMOS Smart Temperature Sensor An Overview,” IEEE Sensors Conference, vol. 2, June 2002, pp. 1423-1427.
    [35] P. Chen, C.-C. Chen, W.-F. Lu and C.-C. Tsai, “A Time-to-Digital-Converter-Based CMOS Smart Temperature Sensor,” IEEE J. Solid-State Circuits, vol. 40, no. 8, pp. 1642-1648, Aug. 2005.
    [36] C.-C. Chen, P. Chen, A.-W. Liu, W.-F. Lu, and Y.-C. Chang, “An Accurate CMOS Delay-Line-Based Smart Temperature Sensor for Low-Power Low-Cost Systems,” Meas. Sci. Technol., vol. 17, no 4, pp. 840-846, Apr. 2006.
    [37] M. G. R. Degrauwe, O. N. Leuthold, E. A. Vittoz, H. J. Oguey, and A. Descombes, “CMOS Voltage References Using Lateral Bipolar Transistors”, IEEE J. Solid-state Circuits, vol. 20, pp. 1151-1157, Dec. 1985.
    [38] R. A. Bianchi, F. Vinci Dos Santos, J. M. Karam, B. Courtois, F. Pressecq, and S. Sifflet, “CMOS compatible temperature sensor based on the lateral bipolar transistor for very wide temperature range application,” Sensors and Actuators, vol. 71, pp. 3-9, 1998.
    [39] G. Wang, and G.C.M. Meijer, “The Temperature Characteristics of Bipolar Transistors Fabricated in CMOS Technology,” Sensors and Actuators, vol. 87, pp.81-89, 2000.
    [40] M. A. P. Pertijs, A. Bakker, and J. H. Huijsing “A high-accury temperature sensor with second-order curvature correction and digital bus interface,” in Proc. IEEE ISCAS, vol. 1, May 2001, pp. 368-371.
    [41] M. A. P. Pertijs, A. Niederkorn, M. Xu; B. McKillop, A. Bakker, and J. H. Huijsing, "A CMOS Temperature Sensor with a 3σ Inaccuracy of ±0.5C from –50C to 120C," in Proc. IEEE ISSCC, vol. 1, Feb. 2003, pp. 200-201.
    [42] M. A. P. Pertijs, A. Niederkorn, M. Xu; B. McKillop, A. Bakker, and J. H. Huijsing, “A CMOS Temperature Sensor with a 3σ Inaccuracy of ±0.5°C from –50°C to 120°C,” IEEE J. Solid-State Circuits, vol. 40, pp. 454-461, Dec. 2005.
    [43] T. A. Demassa, and Z. Ciccone,” Digital Integrated Circuits,” John Wiley & Sons, Inc., 1996.
    [44] I. M. Filanovsky and A. Allam, “Mutual Compensation of Mobility and Threshold Voltage Temperature Effects with Applications in CMOS Circuits,” IEEE Transactions, Circuits and Systems I, vol. 48, no. 7, pp. 876 - 884, July 2001.
    [45] I. M. Filanovsky, “Voltage Reference Using Mutual Compensation of Mobility and Threshold Voltage Temperature Effects,” in Proc. IEEE ISCAS, vol. 5, pp. 197-200, May 2000.
    [46] G. S. Gildenblat and C.-L. Huang, "N-channel MOSFET model for the 60-300-K temperature range," IEEE Transactions on CADICS, vol. 10, pp. 512-518, Apr. 1991.
    [47] R. B. Staszewski, S. Vemulapalli, P. Vallur, J. Wallberg, and P. T. Balsara, “Time-to-Digital Converter for RF Frequency Synthesis in 90 nm CMOS,” IEEE Transaction on Circuits and Systems II: Express Briefs, vol. 53, no. 3, pp. 220-224, Mar. 2006.
    [48] P. Palojarvi, K. Maatta, and J. Kostamovaara, “Integrated Time-of-Flight Laser Radar,” IEEE Transactions on Instrumentation and Measurement, vol. 46, pp. 996-999, Aug. 1997.
    [49] J. Rapeli, T. Rahkonen, and J. Kostamovaara, “Method and circuitry for demodulation of angle modulated signals by measuring cycle time,” US Patent 5,270,666, Dec. 1993.
    [50] K. Park and J. Park, “20 ps resolution time-to-digital converter for digital storage oscilloscopes,” IEEE Nuclear Science Symposium 1998 record, vol. 2, Nov. 1998, pp. 876– 881.
    [51] E. Räisänen-Ruotsalainen, T. Rahkonen, and J. Kostamovaara, “A Low-Power CMOS Time-to-Digital Converter,” IEEE J. Solid-State Circuits, vol. 30, no. 9, pp. 984-990, Sept. 1995.
    [52] K. Karadamoglou, N. P. Paschalidis, E. Sarris, N. Stamatopoulos, G. Kottaras, and V. Paschalidis, “An 11-bit high-resolution and adjustable-range CMOS time-to-digital converter for space science instruments,” IEEE J. Solid-State Circuits, vol.39, no.1, pp. 214-222, Jan. 2004.
    [53] P. Chen, S.-I. Liu, and J. Wu, “A CMOS Pulse-Shrinking Delay Element For Time Interval Measurement,” IEEE Transactions, Circuits and Systems II, vol. 47, no. 9, pp.954-8, Sept. 2000.
    [54] J.-P. Jansson, A. Mantyniemi and J. Kostamovaara “A CMOS time-to-digital converter with better than 10 ps single-shot precision,” IEEE J. Solid-State Circuits, vol. 41, no. 6, pp. 1286-1296, Jun. 2006.
    [55] P. Chen, C.-C. Chen, J.-C. Zheng, and Y.-S. Shen, “A PVT Insensitive Vernier-Based Time-to-Digital Converter with Extended Input Range and High Accuracy,” IEEE Trans. Nucl. Sci., vol. 54, no. 2, pp. 294-302, Apr. 2007.
    [56] K.-H. Cheng and W.-B. Yang, “A low power, wide operating frequency and high noise immunity half-digital phased-locked loop,” in Proc. IEEE Asia-Pacific Conference, Nov. 2002, pp. 263-266.
    [57] P. Chen, C.-C. Chen, T.-K. Chen, and S.-W. Chen, “A Time-Domain Mixed-Mode Temperature Sensor with Digital Set-Point Programming,” in Proc. IEEE CICC, Sept. 2006, pp.821-824.
    [58] O. I. Mohamed, S. Shoji, and K. Watanabe, “A digitally programmable temperature controller based on a phase-locked loop,” IEEE Trans. Instrum. Meas., vol. 37, no. 4, pp. 582-585, Dec. 1988.
    [59] A. Paul Brokaw, “A Temperature Sensor with Single Resistor Set-Point Programming,” IEEE J. Solid–State Circuits, vol.31, no. 12, pp. 1908-1915, Dec. 1999.
    [60] T. Yasuda, “On-Chip Temperature Sensor with High Tolerance for Process and Temperature Variation,” in Proc. IEEE ISCAS, pp. 1024-1027, May 2005.
    [61] Christopher W. Branson, “Integrated Pin Electronics for a VLSI test system,” IEEE Trans. on Industrial Electronics, vol. 36, no. 2, pp. 23-27, May. 1989.
    [62] R.-J. Yang, K.-H. Chao, S.-C. Hwu, C.-K. Liang, and S.-L. Liu, “A 155.52Mbps~3.125Gbps Continuous-Rate Clock and Data Recovery,” IEEE J. Solid-State Circuits, vol. 41, no. 6, pp. 1380-1390, Jun. 2006.
    [63] Y.-L. Tsao, M.-C. Chung, and S.-J. Jou, “Delay-Difference DLL and its application on skewed output buffers,” in Proc, IEEE 3rd Asia-Pacific Conference, Aug. 2002, pp. 279-282.
    [64] G. C. Moyer, M. Clements, W.-T. Liu, T. Schaffer, and R. K. Cavin , “The delay vernier pattern generation technique,” IEEE J. Solid-State Circuits, vol. 32, no. 8, pp. 551-562, Apr. 1997.
    [65] P. Dudek, S. Szczepanski and J. V. Hatfield, “A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line,” IEEE J. Solid-State Circuits, vol. 35, no. 2, pp. 240-247, Feb. 2000.
    [66] J. A. Gasbarro and M. A. Horowitz, “Integrated Pin Electronic for VLSI functional testers,” IEEE J. Solid-State Circuits, vol. 24, no. 2, pp. 331~337, Apr. 1989.
    [67] C.-H. Lin and K. Bult, “A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2,” IEEE J. Solid–State Circuits, vol.33, no. 12, pp. 1948-1958, Dec. 1998.
    [68] M. G. Johnson and M. E. Hudson, “A variable delay line PLL for CPU processor synchronization,” IEEE J. Solid-State Circuits, vol. 23, no. 10, pp. 1218-1223, Oct. 1988.
    [69] J. Christiansen, “An integrated high resolution CMOS timing generator based on an array of the delay lock loops,” IEEE J. Solid-State Circuits, vol. 31, no. 6, pp. 952-957, July. 1996.
    [70] A. Hatakeyama, H. Mochizuki, T. Aikawa, M. Takita, Y. Ishii, H. Tsuboi, S.-Y. Fujioka, S. Yamaguchi, M. Koga, Y. Serizawa, K. Nishimura, K. Kawabata, Y. Okajima, M. Kawano, H. Kojima, K. Mizutani, T. Anezaki, M. Hasegawa, and M. Taguchi, “A 256-Mb SDRAM using a register-controlled digital DLL,” IEEE J. Solid-State Circuits, vol. 32, no. 11, pp. 1728-1734, Nov. 1997.
    [71] F. Lin, J. Miller, A. Schoenfeld, M. Ma, and R. J. Baker, “A register-controlled symmetrical DLL for double-data-rate DRAM,” IEEE J. Solid-State Circuits, vol. 34, no. 4, pp. 565-568, Apr. 1999.
    [72] H. Sutoh, K. Yamakoshi, and M. Ino, “Circuit technique for skew-free clock distribution,” in Proc. IEEE CICC, May 1995, pp. 163-166.
    [73] H. Sutoh and K. Yamakoshi, “A clock distribution technique with an automatic skew compensation circuit,” IEICE Trans. Electron., vol. E81-C, no. 2, pp. 277-283, Feb. 1998.
    [74] G.-K. Dehng, J.-M. Hsu, C.-Y. Yang, and S.-I. Liu, “Clock-deskew buffer using a SAR-controlled delay-locked loop,” IEEE J. Solid-State Circuits, vol. 35, no. 8, pp. 1128-1136, Aug. 2000.
    [75] A. Syed, E. Ahmed, D. Maksimovic, and E. Alarcon, “Digital Pulse Width Modulator Architectures,” in Proc. 35th Annual IEEE Power Electronics Specialirls Conference, 2004, pp. 4689-4695.
    [76] J.-Y. Chueh, “A Delay Locked Loop Using Modified Binary Search Algorithm,” Master thesis, National Taiwan University. Taiwan, 2000.
    [77] G.-K. Dehng, “Implementation and Application of CMOS DLL/PLL”, Ph.D. dissertation, National Taiwan University. Taiwan, 2001.
    [78] O. Trescases, G. Wei and W. T. Ng, “A Segmented Digital Pulse Width Modulator with Self-Calibration for Low-Power SMPS,” in Proc. IEEE Conference on Electron Devices and Solid-State Circuits, Dec. 2005, pp.367-370.
    [79] A. Rossi and G. Fucilli, “Nonredundant successive approximation register for A/D converters,” Electron. Lett., vol. 32, no. 12, pp. 1055–1057, June 1996.

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