本論文係有關雙埠SRAM內建自我測試演算法驗證系統之設計與實現，相關研究工作包含四大部分：
第一部份為探討雙埠SRAM內建自我測試演算法驗證系統之結構，在分析其待測電路特性並考量驗證系統的故障植入與內建自我測試演算法後，發展出雙埠SRAM內建自我測試演算法驗證系統。
第二部份為設計與實現雙埠SRAM內建自我測試演算法驗證系統之硬體，其中包含了雙埠SRAM、故障植入及故障偵測等之電路設計，使能估算故障涵蓋率。最後，將以上設計之硬體整合於單晶片可程式化邏輯陣列中，並以Altera FPGA開發板實現之。
第三部份是驗證系統之軟/硬體整合設計與實現，包含撰寫Nios II相關驅動程式與使用Nios II IDE來驗證其功能。
第四部份是分別以軟、硬體模擬來驗證驗證系統之執行效能。
整體而言，本論文係以研究與設計雙埠SRAM內建自我測試演算法驗證系統為目標，並將其實現於FPGA開發板上。經由各種不同容量大小SRAM做實驗，本論文證實以硬體模擬來驗證內建自我測試演算法有遠勝於軟體模擬的效能。

This thesis is related to the design and implementation of a FPGA-based verification system for BIST (Built-In Self-Test) algorithms of two-port SRAMs. The related research work includes four parts:
The first part is to explore the architecture for the verification system of the two-port SRAM BIST algorithms. After analyzing the property of the circuit under test and considering about fault injection and the BIST algorithms related to the verification system, a verification system for the BIST algorithms of two-port SRAMs has been developed.
The second part is to design and implement the hardware for the verification system of the two-port SRAM BIST algorithms. This research work consists of designing circuits for two-port SRAM, fault injection, and fault detection. Therefore fault coverage can be evaluated. Finally the hardware designed above are integrated onto a single-chip field programmable gate array and implemented on an Altera FPGA development board.
The third part is about the hardware/software co-design and implementation of the verification system. Here Nios-II-related drivers are written and the Nios II IDE (Integrated Development Environment) is used to verify the function of the verification system.
The fourth part is to use both the software and hardware simulation to verify the run-time performance of the verification system.
On the whole, the goal of this thesis is to do researches on the design of a verification system for the two-port SRAM BIST algorithms. Meanwhile the verification system has been implemented on the FPGA development board. After being experimented with SRAMs of various sizes this thesis has demonstrated that hardware simulation (or emulation) can be much more efficient than software simulation in the process of verifying the correctness of the BIST algorithms.

[1] 張逸偉, Design and Automatic Generation for Universal Memory Built-In Self-Test System, 國立成功大學電機工程研究所, 民國九十四年。

[2] 陳鶴仁, SOPC-based演算處理器驗證系統之硬體設計, 國立台灣
科技大學碩士學位論文, 民國九十五年。

[3] 黃耀陞, 文件影像旋轉演算處理器之軟/硬整合設計與實現, 國立台灣科技大學碩士學位論文, 民國九十九年。

[4] A. J. van de Goor, “Testing Semiconductor Memories: Theory and Practice”, ComTex Publishing, Gouda, The Netherlands, 1998; ISBN 90-804276-1-6.

[5] A. J. van de Goor and S. Hamdioui, “Fault Models and Tests for
Two-Port Memories”, Proc. IEEE VLSI Test Symp., pp. 401-410,
1998.

[6] Altera Corporation, Avalon Bus Specification Reference Manual,
2010.

[7] Altera Corporation, Cyclone Device Handbook, Volume 1, 2003.

[8] Altera Corporation, Nios Development Board Stratix II Edition
Reference Manual, 2007.

[9] Altera Corporation, Quartus II Handbook, 2010.

[10] Artisan Standard Library SRAM Generator User Manual, 2005.
[11] IEEE Standard 1364.1 TM -2002, IEEE Standard for Verilog Register
Transfer Level Synyhesis.

[12] L. T. Wang, Cheng-Wen Wu, Xiaoqing Wen, VLSI test
principles and architectures, Elsevier Morgan Kaufmann Publishers, c2006.

[13] L. Yu, Jeffrey Hung, Boryau Sheu, Bill Huynh, Loc Nguyen, Shianling Wu, Laung-Terng Wang and Xiaoqing Wen, “Hybrid Built-In Self-Test Architecture for Multi-port Static RAMs”, Proc. IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems(DFT), 2010.

[14] M. I. Masnita, W. H. W. Zuha, R. M. Sidek and A. H. Izhal,
“March-based SRAM diagnostic algorithm for distinguishing
Stuck-At and transition faults”, IEICE Electronics Express, Vol.6,
No15, 1091-1097, 2009.

[15] M. S. Abadir and J. K. Reghbati, “Functional Testing of Semiconductor Random Access Memories”, ACM Computing Surveys, 15(3), 1983, pp. 175-198.

[16] Memory Testing and Built-In Self-Test, Lab for Dependable and
Secure Computing (LaDSC), EE, NTUST.

[17] M. D. Ciletti, Advanced Digital Design with the Verilog HDL,
Prentice-Hall, 2003.

[18] P.Ellervee, J. Raik, K. Tammemae and R.-J. Ubar, “FPGA-based fault emulation of synchronous sequential circuits” Proc. IET Comput. Digit. Tech, pp.70-76, 2007.

[19] Q. L. Rao, Chun He and Yu-Ming Jia, “A Memory Built-In
Self-Test Architecture for memories different in size”, IEEE 2009.

[20] RAM Fault models and Memory Testing, Cheng-Wen Wu, Lab for
reliable computing (LaRC), EE, NTHU.

[21] S. Di Carlo, P. Prinetto, A. Scionti, and Z. Al-Ars. “Automating
defects simulation and fault modeling for SRAMs”. In High Level
Design Validation and Test Workshop, 2008. HLDVT ’08. IEEE
International, pages 169–176, nov. 2008.