簡易檢索 / 詳目顯示

研究生: 游大慶
Ta-Ching Yu
論文名稱: 一個基於TLC快閃記憶體的保留錯誤、讀取干擾錯誤和霍夫曼編碼之協調方法
CRRC: Coordinating Retention Errors, Read Disturb Errors and Huffman Coding on TLC NAND Flash Memory
指導教授: 吳晋賢
Chin-Hsien Wu
口試委員: 陳雅淑
Ya-Shu Chen
謝仁偉
Jen-Wei Hsieh
修丕承
Pi-Cheng Hsiu
吳晋賢
Chin-Hsien Wu
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2021
畢業學年度: 109
語文別: 英文
論文頁數: 61
中文關鍵詞: 快閃記憶體霍夫曼編碼可靠度保留錯誤讀取干擾錯誤
外文關鍵詞: NAND Flash Memory, Huffman Coding, Reliability, Retention Errors, Read Disturb Errors
相關次數: 點閱:293下載:8
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報

  • Nowadays, TLC NAND flash memory has become a mainstream storage medium because of its large capacity and low cost. However, TLC NAND flash memory could have the reliability problem (such as the retention errors and the read disturb errors), as the cell capacity increases. Because the reasons of the retention errors and the read disturb errors are due to 8 different states in a TLC cell, we will propose a method to coordinate the retention errors, the read disturb errors and the Huffman coding on TLC NAND flash memory by removing some unsuitable states when different data accesses are considered. According to the experimental results, the proposed method can utilize the compression of the Huffman coding to improve the performance. In addition, the proposed method can also remove the unsuitable states that are susceptible to the retention errors or the read disturb errors to enhance the reliability of TLC NAND flash memory.

    Abstract Contents List of Figures List of Tables List of Algorithms 1 Introduction 2 Background Knowledge and Related Works 1 TLC NAND Flash Memory 2 Retention Errors 3 Read Disturb Errors 4 Huffman Coding with TLC NAND Flash Memory 3 Motivation 4 Coordinating Retention Errors, Read Disturb Errors and Huffman Coding 1 System Architecture 2 Relationship between Retention Errors, Read Disturb Errors and Huffman Coding 2.1 From the Viewpoint of Retention Errors 2.2 From the Viewpoint of Read Disturb Errors 2.3 From the Viewpoint of Huffman Coding 3 Relationship between nLC Huffman Coding and Error Mitigation 4 Coordinating Retention Errors, Read Disturb Errors and nLC Huffman Coding 4.1 When cWcR Data are Considered 4.2 When hWcR Data are Considered 4.3 When cWhR Data are Considered 4.4 When hWhR Data are Considered 5 Cooperation with FTL 5.1 Write Operations 5.2 Read Operations 5 Performance Evaluation 1 Experimental Environment 1.1 Experimental Data 1.2 VSSIM Setup 2 Distribution Counts of States before and after nLC Huffman Codings 3 Runtime Results under VSSIM 3.1 Three Runtime Workloads 3.2 INSTALL 3.3 TPC­C 3.4 KERNEL 6 Conclusions References

    [1] R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, “Introduction to flash memory,” Proceedings of
    the IEEE, vol. 91, pp. 489–502, April 2003.
    [2] S. Lee, J.­y. Lee, I.­h. Park, J. Park, S.­w. Yun, M.­s. Kim, J.­h. Lee, M. Kim, K. Lee, T. Kim, et al.,
    “7.5 a 128gb 2b/cell nand flash memory in 14nm technology with tprog= 640µs and 800mb/s i/o
    rate,” in 2016 IEEE International Solid­State Circuits Conference (ISSCC), (San Francisco, CA, USA),
    pp. 138–139, IEEE, 2016.
    [3] K. Fukuda, Y. Watanabe, E. Makino, K. Kawakami, J. Sato, T. Takagiwa, N. Kanagawa, H. Shiga,
    N. Tokiwa, Y. Shindo, et al., “A 151mm 2 64gb mlc nand flash memory in 24nm cmos technology,”
    in 2011 IEEE International Solid­State Circuits Conference, (San Francisco, CA, USA), pp. 198–199,
    IEEE, 2011.
    [4] J.­W. Im, W.­P. Jeong, D.­H. Kim, S.­W. Nam, D.­K. Shim, M.­H. Choi, H.­J. Yoon, D.­H. Kim, Y.­S.
    Kim, H.­W. Park, et al., “7.2 a 128gb 3b/cell v­nand flash memory with 1gb/s i/o rate,” in 2015 IEEE
    International Solid­State Circuits Conference­(ISSCC) Digest of Technical Papers, (San Francisco,
    CA, USA), pp. 1–3, IEEE, 2015.
    [5] T. Tanaka, M. Helm, T. Vali, R. Ghodsi, K. Kawai, J.­K. Park, S. Yamada, F. Pan, Y. Einaga, A. Ghalam, et al., “7.7 a 768gb 3b/cell 3d­floating­gate nand flash memory,” in 2016 IEEE International
    Solid­State Circuits Conference (ISSCC), (San Francisco, CA, USA), pp. 142–144, IEEE, 2016.
    [6] Y. Cai, S. Ghose, E. F. Haratsch, Y. Luo, and O. Mutlu, “Error characterization, mitigation, and recovery in flash­memory­based solid­state drives,” Proceedings of the IEEE, vol. 105, no. 9, pp. 1666–
    1704, 2017.
    [7] K. Mizoguchi, T. Takahashi, S. Aritome, and K. Takeuchi, “Data­retention characteristics comparison of 2d and 3d tlc nand flash memories,” in 2017 IEEE International Memory Workshop (IMW),
    (Monterey, CA, USA), pp. 1–4, IEEE, 2017.
    [8] Q. Li, M. Ye, T.­W. Kuo, and C. J. Xue, “How the common retention acceleration method of 3d nand
    flash memory goes wrong?,” in Proceedings of the 13th ACM Workshop on Hot Topics in Storage and
    File Systems, HotStorage ’21, (New York, NY, USA), p. 1–7, Association for Computing Machinery,
    2021.
    [9] K. Ha, J. Jeong, and J. Kim, “An integrated approach for managing read disturbs in high­density nand
    flash memory,” IEEE Transactions on Computer­Aided Design of Integrated Circuits and Systems,
    vol. 35, no. 7, pp. 1079–1091, 2016.
    [10] J. Li, B. Huang, Z. Sha, Z. Cai, J. Liao, B. Gerofi, and Y. Ishikawa, “Mitigating negative impacts of
    read disturb in ssds,” ACM Trans. Des. Autom. Electron. Syst., vol. 26, Sept. 2020.
    [11] C.­H. Wu, H.­W. Zhang, C.­W. Liu, T.­C. Yu, and C.­Y. Yang, “A dynamic huffman coding method
    for reliable tlc nand flash memory,” ACM Trans. Des. Autom. Electron. Syst., vol. 26, June 2021.
    [12] H. Watanabe, Y. Deguchi, and K. Takeuchi, “Mlc/3lc nand flash ssd cache with asymmetric error
    reduction huffman coding for tiered hierarchical storage,” in 2017 IEEE Asian Solid­State Circuits
    Conference (A­SSCC), pp. 157–160, Nov 2017.
    [13] Y. Cai, Y. Luo, E. F. Haratsch, K. Mai, and O. Mutlu, “Data retention in mlc nand flash memory:
    Characterization, optimization, and recovery,” in 2015 IEEE 21st International Symposium on High
    Performance Computer Architecture (HPCA), pp. 551–563, IEEE, 2015.
    [14] J.­D. Lee, J.­H. Choi, D. Park, and K. Kim, “Degradation of tunnel oxide by fn current stress and its
    effects on data retention characteristics of 90 nm nand flash memory cells,” in 2003 IEEE International
    Reliability Physics Symposium Proceedings, 2003. 41st Annual., (Dallas, TX, USA), pp. 497–501,
    IEEE, 2003.
    [15] R. Micheloni, A. Marelli, and K. Eshghi, Inside solid state drives (SSDs), vol. 37. 01 2018.
    [16] Y. Luo, S. Ghose, Y. Cai, E. F. Haratsch, and O. Mutlu, “Improving 3d nand flash memory lifetime by
    tolerating early retention loss and process variation,” Proceedings of the ACM on Measurement and
    Analysis of Computing Systems, vol. 2, no. 3, pp. 1–48, 2018.
    [17] D. A. Huffman, “A method for the construction of minimum­redundancy codes,” Proceedings of the
    IRE, vol. 40, pp. 1098–1101, Sep. 1952.
    [18] S. Tanakamaru, Y. Kitamura, S. Yamazaki, T. Tokutomi, and K. Takeuchi, “Application­aware solidstate drives (ssds) with adaptive coding,” in 2014 Symposium on VLSI Circuits Digest of Technical
    Papers, (Honolulu, HI, USA), pp. 1–2, June 2014.
    [19] Y. Seo, J. Yun, W. Lee, and D. Jung, “Memory controller, method of operating the same and memory
    system including the same,” Dec. 13 2016. US Patent 9,519,576.
    [20] N.­h. Kim and J.­H. Jang, “Nonvolatile memory device, method of operating nonvolatile memory
    device and memory system including nonvolatile memory device,” June 19 2012. US Patent 8,203,881.
    [21] T. Tanzawa, T. Tanaka, K. Takeuchi, R. Shirota, S. Aritome, H. Watanabe, G. Hemink, K. Shimizu,
    S. Sato, Y. Takeuchi, et al., “A compact on­chip ecc for low cost flash memories,” IEEE Journal of
    Solid­State Circuits, vol. 32, no. 5, pp. 662–669, 1997.
    [22] W. E. Ryan et al., “An introduction to ldpc codes,” 2004.
    [23] K. Zhao, W. Zhao, H. Sun, X. Zhang, N. Zheng, and T. Zhang, “Ldpc­in­ssd: Making advanced error
    correction codes work effectively in solid state drives,” in 11th {USENIX} Conference on File and
    Storage Technologies ({FAST} 13), (San Jose, CA, USA), pp. 243–256, 2013.
    [24] Y. Park and J.­S. Kim, “zftl: Power­efficient data compression support for nand flash­based consumer
    electronics devices,” IEEE transactions on consumer electronics, vol. 57, no. 3, pp. 1148–1156, 2011.
    [25] A. Zuck, S. Toledo, D. Sotnikov, and D. Harnik, “Compression and ssds: Where and how?,” in
    2nd Workshop on Interactions of NVM/Flash with Operating Systems and Workloads (INFLOW 14),
    (Broomfield, CO), USENIX Association, Oct. 2014.
    [26] Y. Liu and W. Wei, “Flap: Flash­aware prefetching for improving ssd­based disk cache,” Journal of
    Networks, vol. 9, no. 10, p. 2766, 2014.
    [27] “Silesia compression corpus..” http://sun.aei.polsl.pl/~sdeor/index.php?page=silesia,
    2020.
    [28] J. Yoo, Y. Won, J. Hwang, S. Kang, J. Choi, S. Yoon, and J. Cha, “Vssim: Virtual machine based ssd
    simulator,” in 2013 IEEE 29th Symposium on Mass Storage Systems and Technologies (MSST), (Long
    Beach, CA, USA), pp. 1–14, 2013.
    [29] F. Bellard, “Qemu, a fast and portable dynamic translator.,” in USENIX annual technical conference,
    FREENIX Track, vol. 41, (Anaheim, CA, USA), p. 46, USENIX, 2005.
    [30] “Micron 3d nand flash memory.” https://www.micron.com/-/media/client/global/
    documents/products/product-flyer/3d_nand_flyer.pdf?la=en, 2020.
    [31] C. Ji, L.­P. Chang, L. Shi, C. Gao, C. Wu, Y. Wang, and C. J. Xue, “Lightweight data compression for
    mobile flash storage,” ACM Transactions on Embedded Computing Systems (TECS), vol. 16, no. 5s,
    pp. 1–18, 2017.
    [32] D. E. Difallah, A. Pavlo, C. Curino, and P. Cudre­Mauroux, “Oltp­bench: An extensible testbed for
    benchmarking relational databases,” Proceedings of the VLDB Endowment, vol. 7, no. 4, pp. 277–288,
    2013.

    QR CODE