近年來隨著科技的發展，人們對於通訊系統的品質與速度之需求日益提升，多輸入多輸出(Multiple Input Multiple Output ; MIMO)通訊技術能夠在不增加使用頻寬的狀況下，大幅提升傳輸品質與效率，使其在現代無線通訊系統中的重要性日益漸長。然而，MIMO 通訊環境之優劣會隨時改變，傳統的系統將無法有效支援隨時改變之通道環境，此外，高速度之通訊應用在未來廣泛發展。因此，如何在MIMO系統中設計出高速度且可以針對不同環境執行最有效率之電路元件便成為現今無線通訊系統之一大挑戰。
進一步來看，訊號偵測器是MIMO 系統中最為重要且運算量最為龐大的運算元件之一。通常一個MIMO 訊號偵測器需要對資料執行預先處理，以QR 分解為最基本的技術。此外，排序QR 分解(Sorted QR)與Minimum Mean-Square Error SQR(MMSE-SQR)分解是QR 分解之延伸技術，因為增加了額外的運算，因此可以更進一步地改善解碼品質。本論文提出一種符合於未來高速且可以同時支援上述三種矩陣分解之預處理器，我們所提出來的可配置預處理器可以平衡解碼品質與功率
消耗。在此設計中，我們基於吉文斯旋轉(Givens Rotation)演算法實現QR 分解，並且基於收縮陣列(Systolic Array)架構以及透過座標旋轉運算法(CORDIC)實現硬體電路。另外，本設計在不同模式下能夠共用相同元件，達到最大的硬體使用率。值得一提的是，我們分析出一種計算範數(Norm)之策略，使得計算範數之硬體面積可以有效降低。最後，本設計基於台積電90 奈米製成環境下實現，電路合成後(prelayout)的結果為每秒可以執行55 百萬個QR / SQR / MMSE-SQR 分解的運算。

This thesis presents the VLSI architecture and circuit implementation of a high-throughput configurable pre-processor for 4×4 Multiple-Input Multiple-Output (MIMO) systems. The proposed configurable pre-processor can support three functions – QR decomposition (QRD), Sorted QRD (SQRD) and Minimum Mean Squared Error SQRD (MMSE-SQRD) by sharing the Process Unit (PU) and transferring the data stream. Furthermore, in order to achieve the goal of high throughput, the proposed design is architected in a pipelined systolic array structure. The proposed configurable architecture provides a choice of a trade-off between the Bit Error Rate (BER) performance and power consumption in MIMO detector processing. Moreover, the channel matrix is operating in two-stage processor: complex-value Givens rotation and real-value Givens rotation in order to reduce the hardware complexity by reducing the computational complexity. Specifically, we proposed a novel norm calculation strategy such that large parts of the norm calculation operators can be reduced. The proposed pre-processor implemented in TSMC 90nm CMOS technology achieves the throughput up to 55 mega per second for decomposing 4×4 channel matrix, and outperforms the related works with equal functionality and architecture.

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