論文中提出了一個符合AXI4介面的管線式AES加解密矽智財設計，注重其核心的面積大小及吞吐量，減少所需硬體資源並提升運算效能。依據AES演算法實現出來的加解密晶片，輸入的每一筆資料為128位元。金鑰部分為可選擇的128位元、192位元及256位元。
為了減少面積使用及提高吞吐量，採用了內部回合管線式(Inner-round pipelining)架構，將加密及解密流程使用的硬體資源結合，達成共享資源的目的。在位元組替代轉換中，使用複合場運算來有效的降低演算法複雜度；混合行運算中，將演算法簡化，並找出相同的運算子來達到電路共享；金鑰擴展程序中，採用了即時運算(On-the-fly)的設計，減少記憶體面積。
在複雜的SoC設計中，需要使用高效能且低延遲的匯流排，所以選擇了目前被業界廣泛使用的ARM公司提出的AMBA 4.0的 Advanced eXtensible Interface (AXI)匯流排。
管線式AES加解密矽智財已經分別在Xilinx 的Virtex 5系列FPGA (XC5VLX110T)以及TSMC 0.18μm 元件庫 (Cell Library)上實現與驗證。在FPGA設計部分，使用2562個暫存器與4829個LUTs，工作頻率為200 MHz，資料處理量最高為2327 Mbps；在元件庫設計部分，工作頻率為142.85 MHz，晶片核心(core)面積為874.145 μm × 872.265 μm，資料處理量最高為 1662 Mbps，其等效閘數量 (gate count)約為48537個，消耗功率為33.43 mW。

In this thesis, a pipelined architecture of AES Encryption/Decryption based on AXI4 interface is proposed. This architecture emphasizes area and throughput, reduces hardware cost and improves its computing performance. According to the AES algorithm, the input data is 128 bits and the cipher key has three options: 128, 192 or 256 bits.
In order to reduce area and improve its computing performance, we use an inner-round pipelining architecture, combining Encryption and Decryption to share hardware. The composite field arithmetic is used in Subbytes transformation. Simplify the algorithm by finding the same operators for Mixcolumn/Invmixcolumn transformation. An on-the-fly key architecture is used in KeyExpansion to reduce area of memory.
In complex SoC design, it often needs a bus, which has high performance and low latency. Therefore, we select AMBA4.0 AXI interface, which is widely used in industry.
The pipeline architecture of AES Encryption/Decryption IP has been implemented and verified with both Xilinx Virtex 5 (XC5VLX110T) and TSMC 0.18 µm cell library. In the FPGA part, it uses 2562 registers and 4829 LUTs, operates at 200 MHz and can achieve a high throughput of 2327 Mbps. In the cell-based part, it operates at 142.85 MHz and can achieve a high throughput of 1662 Mbps. The core occupies an area of 874.145 µm × 872.265 µm, which is approximately equivalent 48537 gates, and consumes about 33.43 mW in the typical operating condition.

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