本論文係有關兩階段直線偵測霍夫轉換演算處理器之軟/硬體整合設計與驗證，相關研究工作包含四大部分：
第一部份為HT-based直線偵測演算法之軟體設計，在分析其特性並考量嵌入式硬體系統資源的限制後，發展出HT-based直線偵測兩階段演算法。
第二部份為設計與實現兩階段直線偵測霍夫轉換演算處理器，同步動態記憶體被用以儲存完整影像，因此處理器的設計包含了來源資料提取副處理器、霍夫轉換副處理器及尋找區域最大值副處理器。最後，將以上設計之硬體整合於SOPC系統中，並以Altera FPGA開發板實現之。
第三部份是撰寫演算處理器之相關驅動程式，再使用RPC-based驗證系統來驗證其功能。
第四部份是演算處理器之驗證與執行效能之評估。
整體而言，本論文係以研究兩階段直線偵測霍夫轉換演算法與設計其處理器為目標，並將其實作於FPGA開發板上。經各種不同的影像實驗，證實本論文所發展的演算法有極佳的效果，其相關之軟/硬整合設計方法，亦可改善演算處理器設計與驗證流程之效率。

This thesis is related to the hardware/software co-design and verification of an algorithmic processor for an HT-based (Hough- Transform-based) two-stage line detection algorithm. The related research work includes four parts:
The first part is about software design of the HT-based line detection algorithm for binary images. After analyzing the property of the HT-based algorithm and considering about the limited hardware resources in the embedded system, a two-stage HT-based algorithm for line detection has been developed.
The second part is to design and implement a two-stage algorithmic processor for HT-based line detection. SDARM is used to store the whole binary images. Therefore the processor consists of source data fetching sub-processor, Hough transform sub-processor, and local max finding sub-processor. Finally, the above hardware modules are integrated into an SOPC-based system and implemented on an Altera FPGA development board.
The third part is to write the related drivers for the algorithmic processor. Then the function of the algorithmic processor is verified through using a RPC-based verification system.
The fourth part is about the verification and the evaluation of the run-time performance of the algorithmic processor.
On the whole, the goal of this thesis is to do researches on the development of an HT-based two-stage line detection algorithm and its hardware processor. Then the related algorithmic processor is developed and implemented on the FPGA development board. After being verified by using various images, the algorithm developed in this thesis has shown very good performance. Meanwhile, it also shows that the hardware/software co-design method presented can improve the efficiency of both the design and verification flows.

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