本文透過影像處理技術偵測與辨識道路上之速限標誌，針對用路者常忽略道路上速限標誌可能造成的危害，給予必要的提醒及警示。現有文獻所提出的即時交通標誌偵測與辨識大多使用軟體的方法來解決，其不但處理時資料量龐大，硬體設備的需求也相對提高。因此，本文提出軟硬體共設計方法，將速限標誌辨識功能實現於FPGA上，大量的規則計算可以以硬體平行處理。因此，可以即時的偵測標誌所在位置及辨識速限。

在交通標誌偵測中，使用簡單的CIE彩色模型，精準找到標誌紅色外框特徵，並透過圖像灰階值來取得標誌速限內容；為了避免雜訊干擾辨識，透過二十五宮格統計方法來達成雜訊消除與圖像邊緣平滑化；最後，將圖形邊緣分為順時針、逆時針及直線三個狀態，透過這三個狀態來快速的辨識出圖像內容。

This thesis is aimed at detecting and recognizing the speed limit signs in time with image processing techniques. It will give the necessary reminders and warning to the drivers who may ignore the speed limit signs. In the existing literatures, most of proposed schemes for real-time traffic sign detection and recognition employed software approach. It not only has a large amount of data processing, but also requires a high demand of hardware. Therefore, this thesis proposes a hardware-software co-design scheme on FPGA, where regular computations are processed parallel with hardware, resulting in detecting and recognizing speed limit signs in real-time.

In the propose scheme, the CIE color model is employed to precisely locate the red ring of speed limit signs, while speed limit can be recognized with gray values. In order to avoid noise interference, the twenty-five grids method is used for noise reduction and edge smoothing. Then, the edge of a pattern is segmented into clock-wise curve segments, counter-clock-wise curve segments and line segments, resulting in recognizing the patterns quickly.

The experiments show that our proposed method can detect and recognize a speed limit sign in 63ms.

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