研究生: |
蘇建云 Jian-Yun Su |
---|---|
論文名稱: |
以FPGA實現即時表情辨識系統 A Real-Time Facial Expression Recognition System Implemented on FPGA |
指導教授: |
王乃堅
Nai-Jian Wang |
口試委員: |
蘇順豐
Shun-Feng Su 鍾順平 Shun-Ping Chung 呂學坤 Shyue-Kung Lu 郭景明 Jing-Ming Guo |
學位類別: |
碩士 Master |
系所名稱: |
電資學院 - 電機工程系 Department of Electrical Engineering |
論文出版年: | 2020 |
畢業學年度: | 108 |
語文別: | 中文 |
論文頁數: | 82 |
中文關鍵詞: | FPGA 、人臉偵測 、表情辨識 、即時 |
外文關鍵詞: | FPGA, Face detection, Facial expression recognition, real-time |
相關次數: | 點閱:328 下載:0 |
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近年來,人們積極的研究人類與機器的互動方式,從早期的滑鼠、鍵盤和觸控裝置,到新興的指紋、手勢等等,互動的方式越來越多元及人性化,本論文即時表情辨識系統為一個人機互動系統,透過影像處理的方式,從攝影機擷取影像進行人臉偵測與表情辨識,並顯示辨識結果於螢幕上。
本論文提出一個以純硬體的數位電路來實現即時表情辨識系統,此系統分為兩大部分:(1)軟體端的前置作業,(2)硬體端的實際運作。軟體端的前置作業主要為以機器學習(Machine Learning)的方式訓練出硬體端所需要的人臉偵測與表情辨識的分類器。主要分為三個步驟:(1)人臉特徵提取,(2)閾值型/查表型弱分類器,(3)AdaBoost/Multi-Class AdaBoost演算法。在硬體端的實際運作主要分為三個步驟:(1)人臉候選區域擷取,(2)人臉偵測,(3)表情辨識,將這些步驟分別設計成硬體電路模組,此系統使用Verilog硬體描述語言(Hardware Description Language)以純硬體的方式設計,並在Altera DE2-115多媒體開發平台實現。
實驗結果顯示此系統使用了79,316 (69%)個邏輯元件(logic elements)和1,806,350 (45%) bits內部記憶體,系統辨識率為78.2%,且處理速度達每秒68張影像(NTSC Input)。
In recent years, people have actively studied the interaction between humans and machines. From the mouse and keyboard to fingerprints and gestures, interactive methods are becoming more and more diverse and humanized. Therefore, we proposed a real-time facial expression recognition system implemented on FPGA. This system is applied to human-computer interaction. Through image processing, the image captured from the camera is used to detect faces and recognize the expression on the face. After that, the recognition result is displayed on the screen.
In this thesis, our system is divided into two parts: (1) Off-line training work on PC environment, (2) Real-time processing implemented on FPGA. The classifiers needed for face detection and facial expression recognition on the FPGA are trained by PC-based Machine Learning. The training consists of three steps: (1) MB-LBP features extraction, (2) Weak classifiers (Threshold or Look-Up-Table), (3) Multi-Class AdaBoost algorithm. There are three steps in real-time processing: (1) Face candidate extraction, (2) Face detection, (3) Facial expression recognition. Each step is designed and modularized with Verilog HDL.
The experimental results show that our system requires 79,316 logic elements and 1,806,350 bits memory, which is about 69% of total logic elements and 45% of total memory. The whole system is designed on Altera DE2-115 which can process up to 68 frames per second at an operating frequency of 27.03MHz with 78.2% accuracy.
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